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FDC6312P - onsemi

Description: SuperSOT™-6 package: small footprint (72%smaller than standard SO-8); low profile (1mm thick); High performance trench technology for extremely low RDS(ON); RDS(ON) = 155 mΩ @ VGS = –2.5 V; RDS(ON) = 115 mΩ @ VGS = –4.5 V; –2.3 A, –20 V. ; RDS(ON) = 225 mΩ @ VGS = –1.8 V

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PCB Footprints
FDC6312P - onsemi PCB footprint - SOT23 (6-Pin) - SOT23 (6-Pin) - TSOT-23 CASE419AG-01 ISSUE O
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3D Models
FDC6312P - onsemi  - 3D model - SOT23 (6-Pin) - TSOT-23 CASE419AG-01 ISSUE O
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FDC6312P Details

  • Manufacturer Part Number:

    FDC6312P

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    TSOT-23-6

  • Manufacturer Package Code:

    419BL

  • Country Of Origin:

    Philippines

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    11 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    6.9

  • Configuration:

    SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    20 V

  • Drain Current-Max (ID):

    2.3 A

  • Drain-source On Resistance-Max:

    0.115 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • JESD-30 Code:

    R-PDSO-G6

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    2

  • Number of Terminals:

    6

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    150 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    P-CHANNEL

  • Power Dissipation-Max (Abs):

    0.96 W

  • Qualification Status:

    Not Qualified

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    GULL WING

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

FDC6312P Frequently Asked Questions (FAQs)

  • A good PCB layout for the FDC6312P involves keeping the input and output traces separate, using a solid ground plane, and placing the device close to the power source. Additionally, using a shielded cable for the output and keeping the cable length as short as possible can help minimize EMI.
  • To ensure proper biasing, make sure to connect the EN pin to a voltage source between 2.5V and 5.5V, and the VIN pin to a voltage source between 2.5V and 18V. Also, ensure that the input voltage is stable and within the recommended range to prevent oscillations.
  • The maximum current rating for the FDC6312P is 2A. However, it's recommended to derate the current to 1.5A for continuous operation to ensure reliability and prevent overheating.
  • To protect the FDC6312P from overvoltage and undervoltage conditions, use a voltage regulator or a voltage supervisor to regulate the input voltage. Additionally, consider adding overvoltage protection (OVP) and undervoltage protection (UVP) circuits to prevent damage to the device.
  • To manage thermal issues, ensure good airflow around the device, and consider using a heat sink or thermal pad to dissipate heat. Also, operate the device within the recommended temperature range (-40°C to 125°C) to prevent overheating.

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FDC6312P Overview

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