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FDMS86550 - onsemi

Description: Advanced Package and Silicon combination for low rDS(on) and high efficiency ; RoHS Compliant ; Max rDS(on) = 2.2 mΩ at VGS = 8 V, ID = 27 A ; 100% UIL tested ; MSL1 robust package design ; Max rDS(on) = 1.65 mΩ at VGS = 10 V, ID = 32 A

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PCB Footprints
FDMS86550 - onsemi PCB footprint - Other - Other - FDMS86550-1
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3D Models
FDMS86550 - onsemi  - 3D model - Other - FDMS86550-1
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FDMS86550 Details

  • Manufacturer Part Number:

    FDMS86550

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    PQFN-8

  • Package Description:

    ROHS COMPLIANT, POWER 56, 8 PIN

  • Manufacturer Package Code:

    483AG

  • Country Of Origin:

    Philippines

  • ECCN Code:

    EAR99

  • Manufacturer:

    onsemi

  • YTEOL:

    5.6

  • Avalanche Energy Rating (Eas):

    937 mJ

  • Case Connection:

    DRAIN

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    60 V

  • Drain Current-Max (ID):

    32 A

  • Drain-source On Resistance-Max:

    0.00165 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • JEDEC-95 Code:

    MO-240AA

  • JESD-30 Code:

    R-PDSO-N5

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    1

  • Number of Terminals:

    5

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    150 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    156 W

  • Pulsed Drain Current-Max (IDM):

    320 A

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    NO LEAD

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

FDMS86550 Frequently Asked Questions (FAQs)

  • A good PCB layout for the FDMS86550 involves keeping the high-current paths short and wide, using multiple vias to connect the thermal pad to the heat sink, and placing the input capacitors close to the device.
  • To optimize thermal performance, ensure good thermal contact between the device and the heat sink, use a heat sink with a high thermal conductivity, and keep the ambient temperature as low as possible.
  • The maximum allowed voltage on the VIN pin is 28V, but it's recommended to keep it below 24V for reliable operation.
  • Ensure the EN pin is properly biased to the recommended voltage range (1.5V to 5.5V) and the VCC pin is connected to a stable 5V supply.
  • A 10uF to 22uF X5R or X7R ceramic capacitor is recommended for the input capacitor, placed as close to the VIN pin as possible.

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FDMS86550 Overview

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