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FGH40T120SQDNL4 - onsemi

Description: Extremely Efficient Trench with Field Stop Technology • TJmax = 175°C • Soft Fast Reverse Recovery Diode • Optimized for High Speed Switching • These are Pb−Free Devices

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FGH40T120SQDNL4 - onsemi PCB footprint - Other - Other - TO−247−4LD CASE 340CJ ISSUE O_1
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FGH40T120SQDNL4 Details

  • Manufacturer Part Number:

    FGH40T120SQDNL4

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    TO-247-4

  • Manufacturer Package Code:

    340CJ

  • Country Of Origin:

    Mainland China

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    23 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    5.35

  • Collector Current-Max (IC):

    160 A

  • Collector-Emitter Voltage-Max:

    1200 V

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • Gate-Emitter Thr Voltage-Max:

    6.5 V

  • Gate-Emitter Voltage-Max:

    20 V

  • JEDEC-95 Code:

    TO-247

  • JESD-30 Code:

    R-PSFM-T4

  • JESD-609 Code:

    e3

  • Number of Elements:

    1

  • Number of Terminals:

    4

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    FLANGE MOUNT

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    454 W

  • Surface Mount:

    NO

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Position:

    SINGLE

  • Transistor Application:

    POWER CONTROL

  • Transistor Element Material:

    SILICON

  • Turn-off Time-Nom (toff):

    372 ns

  • Turn-on Time-Nom (ton):

    80 ns

  • VCEsat-Max:

    1.95 V

FGH40T120SQDNL4 Frequently Asked Questions (FAQs)

  • A good starting point is to follow the recommended PCB layout guidelines in the datasheet. For thermal management, ensure a minimum of 2oz copper thickness, use thermal vias, and consider a heat sink or thermal interface material to maintain a junction temperature below 150°C.
  • Implement proper ESD protection measures, such as using ESD-sensitive handling and storage procedures, and incorporating ESD protection devices in the circuit. Also, ensure the device is properly powered up and down to prevent latch-up.
  • Monitor the device's junction temperature, voltage, and current. Implement over-temperature, over-voltage, and over-current protection mechanisms. Regularly inspect the device for signs of wear or degradation.
  • Optimize the gate driver design by selecting a suitable gate driver IC, ensuring proper impedance matching, and using a low-inductance layout. Implement a snubber circuit to reduce EMI and minimize power losses.
  • Perform thorough testing, including characterization of the device's electrical parameters, thermal performance, and reliability. Validate the device's performance under various operating conditions, including temperature, voltage, and frequency.

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