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XC6SLX4-3TQG144C - AMD

Description: IC FPGA 102 I/O 144TQFP

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XC6SLX4-3TQG144C - AMD PCB footprint - Quad Flat Packages - Quad Flat Packages - IO_L51P_3
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XC6SLX4-3TQG144C - AMD  - 3D model - Quad Flat Packages - IO_L51P_3
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XC6SLX4-3TQG144C Details

  • Manufacturer Part Number:

    XC6SLX4-3TQG144C

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    20 X 20 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144

  • Country Of Origin:

    Taiwan

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    12 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    4

  • Clock Frequency-Max:

    862 MHz

  • Combinatorial Delay of a CLB-Max:

    0.21 ns

  • JESD-30 Code:

    S-PQFP-G144

  • JESD-609 Code:

    e3

  • Length:

    20 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    300

  • Number of Inputs:

    100

  • Number of Logic Cells:

    3840

  • Number of Outputs:

    100

  • Number of Terminals:

    144

  • Operating Temperature-Max:

    85 °C

  • Organization:

    300 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFQFP

  • Package Equivalence Code:

    QFP144,.87SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK, LOW PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 40 nm

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    20 mm

XC6SLX4-3TQG144C Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the XC6SLX4-3TQG144C is 350 MHz, but it depends on the specific application and design implementation.
  • You can implement DDR3 memory interface using the Memory Interface Generator (MIG) tool in Vivado Design Suite, which provides a pre-built IP core for DDR3 memory interface.
  • The power consumption of the XC6SLX4-3TQG144C depends on the specific design implementation, but the typical static power consumption is around 1.2W, and the dynamic power consumption can range from 1.5W to 3.5W.
  • Yes, the XC6SLX4-3TQG144C has built-in transceivers that support high-speed serial interfaces like PCIe Gen1/2 and SATA II, with data rates up to 5 Gbps.
  • You can use the ChipScope Pro tool in Vivado Design Suite to debug and test your design on the XC6SLX4-3TQG144C, which provides real-time visibility into the FPGA's internal signals and allows you to set up triggers and capture data.

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XC6SLX4-3TQG144C Overview

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Image Part Number Model
Part Image XC6SLX4-3TQG144I AMD

Field Programmable Gate Array, 300 CLBs, 862MHz, 3840-Cell, CMOS, PQFP144

Part Image XC6SLX4-3TQG144C AMD Xilinx

Field Programmable Gate Array, 300 CLBs, 862MHz, 3840-Cell, CMOS, PQFP144

Part Image XC6SLX4-3TQG144I AMD Xilinx

Field Programmable Gate Array, 300 CLBs, 862MHz, 3840-Cell, CMOS, PQFP144

Part Image XC6SLX4-3TQG144Q AMD Xilinx

Field Programmable Gate Array

Part Image XC6SLX4-3TQG144Q AMD

Field Programmable Gate Array, 300 CLBs, 862MHz, 3840-Cell, PQFP144

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