DRAMs||Other Memory ICs||Flash Memories||SRAMs Footprint, Symbol and 3D Model search results

Showing 25 of 552034 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71V65803S133PFG8 Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65803S133PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V67603S133BQI Renesas Electronics	1	The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.The order of these three addresses are defined by the internal burst counter and the LBO input pin.	BGA	71V67603S133BQI	3D model available Symbol and footprint available 3	1 Download Model
	70V631S10BFG8 Renesas Electronics	1	The 70V631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po	BGA	70V631S10BFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S133BG Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2546S133BG	3D model available Symbol and footprint available 3	1 Download Model

	M48T35-70PC1 STMicroelectronics	1	STMicroelectronics M48T35-70PC1 NVRAM, 32kbit, 70ns, 5V 28-Pin PCDIP	Dual-In-Line Packages	M48T35-70PC1	3D model available Symbol and footprint available 3	1 Download Model
	71V432S5PFG Renesas Electronics	1	The 71V432 3.3V CMOS high-speed CacheRAM is organized as 32K x 32. The pipelined burst architecture provides cost effective 3-1-1-1 secondary cache performance for processors up to 100 MHz. The 71V432 CacheRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the CacheRAM.	Quad Flat Packages	71V432S5PFG	3D model available Symbol and footprint available 3	1 Download Model
	70V657S10BFG8 Renesas Electronics	1	The 70V657 is a high-speed 32K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	BGA	70V657S10BFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V547S80PFG8 Renesas Electronics	1	The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V547S80PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V67903S85PFGI8 Renesas Electronics	1	The 71V67903 3.3V CMOS SRAM is organized as 512K x 18. The 71V67903 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67903S85PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	7132LA35C Renesas Electronics	1	The 7132 is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7142 "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535	Ceramic Dual-In-Line Packages	7132LA35C	3D model not available Symbol and footprint available 2	1 Download Model
	R1QEA7236ABB-19IB1 Renesas Electronics	1	The R1Q#A7236 is a 2, 097, 152-word by 36-bit and the R1Q#A7218 is a 4, 194, 304-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed, low	BGA	R1QEA7236ABB-19IB1	3D model available Symbol and footprint available 3	1 Download Model
	71V321L35PFGI8 Renesas Electronics	1	The 71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	71V321L35PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	70V26L35G Renesas Electronics	1	The 70V26 is a high-speed 16K x 16 Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or wider memory system applications resulting in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Other	70V26L35G	3D model available Symbol and footprint available 3	1 Download Model
	71256L85DB Renesas Electronics	1	The 71256 5V CMOS SRAM is organized as 32K x 8. The circuit also offers a reduced power standby mode for significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability allowing operation off a 2V battery. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	71256L85DB	3D model not available Symbol and footprint available 2	1 Download Model
	71256SA20YG8 Renesas Electronics	1	The 71256SA 5V CMOS SRAM is organized as 32K x 8. All bidirectional inputs and outputs of the 71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71256SA20YG8	3D model available Symbol and footprint available 3	1 Download Model

	71V3577S65PFG8 Renesas Electronics	1	The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V3577S65PFG8	3D model available Symbol and footprint available 3	1 Download Model
	70T3399S200BC Renesas Electronics	1	The 70T3399 is a high-speed 128K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3399 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3399S200BC	3D model available Symbol and footprint available 3	1 Download Model
	71V67803S150PFGI Renesas Electronics	1	The 71V67803 3.3V CMOS SRAM is organized as 512K x 18. The 71V67803 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67803S150PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V3559S85BG8 Renesas Electronics	1	The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3559 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).	BGA	71V3559S85BG8	3D model available Symbol and footprint available 3	1 Download Model
	71V65903S80PFG8 Renesas Electronics	1	The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65903 contain address, data-in and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65903S80PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V547S80PFGI Renesas Electronics	1	The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V547S80PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA166BQ Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA166BQ	3D model available Symbol and footprint available 3	1 Download Model
	70T3319S166BC Renesas Electronics	1	The 70T3319 is a high-speed 256K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3319 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3319S166BC	3D model available Symbol and footprint available 3	1 Download Model
	71V321L25TFG Renesas Electronics	1	The 71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	71V321L25TFG	3D model available Symbol and footprint available 3	1 Download Model
	71V416L15BE8 Renesas Electronics	1	The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	BGA	71V416L15BE8	3D model available Symbol and footprint available 3	1 Download Model
19 20 21 22 23 24 25 26 27

Can't find what you're looking for? Request this part

DRAMs||Other Memory ICs||Flash Memories||SRAMs Model Download Search Results

Popular SRAMs