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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	S25FL164K0XNFI010 Infineon	1	NOR Flash 64M, 3.0V, 108Mhz Serial NOR Flash	Small Outline No-lead	S25FL164K0XNFI010	3D model available Symbol and footprint available 3	1 Download Model
	MT25QL512ABB1EW9-0SIT Micron	1	IC FLASH 512MBIT 108MHZ 8WDFN	Small Outline No-lead	MT25QL512ABB1EW9-0SIT	3D model available Symbol and footprint available 3	1 Download Model
	W25Q64FVSFIQ Winbond	1	IC FLASH 64MBIT 104MHZ 16SOIC	Small Outline Packages	W25Q64FVSFIQ	3D model available Symbol and footprint available 3	1 Download Model
	AM29F016B-120EC AMD	1	Flash Memory IC 16 MEGABIT CMOS FLASH EPROM	Small Outline Packages	AM29F016B-120EC	3D model available Symbol and footprint available 3	1 Download Model

	W25Q64BVSSIP Winbond	1	64M-Bit Serial Flash Memory with Dual & Quad SPI	Small Outline Packages	W25Q64BVSSIP	3D model available Symbol and footprint available 3	1 Download Model
	M25P10-AVMN6TP STMicroelectronics	1	Flash Memory SERIAL SECTOR ERASE FLASH 1MEG	Small Outline Packages	M25P10-AVMN6TP	3D model available Symbol and footprint available 3	1 Download Model
	IS25WP128-JKLE Integrated Silicon Solution Inc.	1	NOR Flash 128Mb QPI/QSPI, WSON, RoHS	Small Outline No-lead	IS25WP128-JKLE	3D model available Symbol and footprint available 3	1 Download Model
	GLS55LC200-60-C-TQWE Greenliant	1	NAND CONTROLLER	Quad Flat Packages	GLS55LC200-60-C-TQWE	3D model available Symbol and footprint available 3	1 Download Model
	72V241L15PFGI8 Renesas Electronics	1	The 72V241 is a 4K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72241 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V241L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	723623L12PFG Renesas Electronics	1	The 723623 is a 256 x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers.	Quad Flat Packages	723623L12PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T18125L6-7BB Renesas Electronics	1	The 72T18125 is a 512K x 18 / 1M x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18125L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72T1885L5BB Renesas Electronics	1	The 72T1885 is a 32K x 18 / 64K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1885L5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V85L15PAG8 Renesas Electronics	1	The 72V85 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V85L15PAG8	3D model available Symbol and footprint available 3	1 Download Model
	72V205L10PFG Renesas Electronics	1	The 72V205 is a 256 x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V205L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L6BB Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V36100L6BB	3D model available Symbol and footprint available 3	1 Download Model

	72V81L15PAG8 Renesas Electronics	1	The 72V81 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V81L15PAG8	3D model available Symbol and footprint available 3	1 Download Model
	72V01L15JG8 Renesas Electronics	1	The 72V01 is a 512 x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V01L15JG8	3D model available Symbol and footprint available 3	1 Download Model
	72V273L7-5PFGI8 Renesas Electronics	1	The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V273L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72215LB15PFGI Renesas Electronics	1	The 72215 is a 512 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain techniqu	Quad Flat Packages	72215LB15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	7205L20DB Renesas Electronics	1	The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7205L20DB	3D model not available Symbol and footprint available 2	1 Download Model
	7206L15JG8 Renesas Electronics	1	The 7206 is a 16K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7206L15JG8	3D model not available Symbol and footprint available 2	1 Download Model
	723632L15PFG Renesas Electronics	1	The 723632 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 512 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723632L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V01L15JG Renesas Electronics	1	The 72V01 is a 512 x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V01L15JG	3D model not available Symbol and footprint available 2	1 Download Model
	72235LB15PFGI Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V851L10PFG8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
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