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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	70V7599S166BF8 Renesas Electronics	1	The 70V7599 is a high-speed 128K x 36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 2Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7599S166BF8	3D model available Symbol and footprint available 3	1 Download Model
	71T75802S200PFGI8 Renesas Electronics	1	The 71T75802 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75802 contains data I/O, address and control signal registers.	Quad Flat Packages	71T75802S200PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	R1QBA7236ABG-20IA0 Renesas Electronics	1	Support is limited to customers who have already adopted these products.DDR II / II+ (Double Data Rate) SRAMs and QDR^(TM) II / II+ (Quad Data Rate) SRAMs are the ideal memory devices for next generation networking and communications systems. These ultra-fast devices can support high bandwidth systems that require memories capable of very high operating frequencies combined with low latencies and full cycle utilization. DDR SRAMs can provide double data rate (DDR) operation on each data pin in write or read	BGA	R1QBA7236ABG-20IA0	3D model available Symbol and footprint available 3	1 Download Model
	71V67603S133BGG8 Renesas Electronics	1	The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.The order of these three addresses are defined by the internal burst counter and the LBO input pin.	BGA	71V67603S133BGG8	3D model available Symbol and footprint available 3	1 Download Model

	70V7339S166BC8 Renesas Electronics	1	The 70V7339 is a high-speed 512K x 18 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 8K x 18 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 8K x 18 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7339S166BC8	3D model available Symbol and footprint available 3	1 Download Model
	7038L20PFGI Renesas Electronics	1	The 7038 is a high-speed 64K x 18 Dual-Port Static RAM designed to be used as a stand-alone 1152K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or more word systems. This MASTER/SLAVE approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	7038L20PFGI	3D model available Symbol and footprint available 3	1 Download Model
	7008L25G Renesas Electronics	1	The 7008 is a high-speed 64K x 8 Dual-Port Static RAM designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Other	7008L25G	3D model available Symbol and footprint available 3	1 Download Model
	71T75602S150BGI8 Renesas Electronics	1	The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75602 contains data I/O, address and control signal registers.	BGA	71T75602S150BGI8	3D model available Symbol and footprint available 3	1 Download Model
	6116SA90TDB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	6116SA90TDB	3D model not available Symbol and footprint available 2	1 Download Model
	70V631S12BFGI Renesas Electronics	1	The 70V631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po	BGA	70V631S12BFGI	3D model available Symbol and footprint available 3	1 Download Model
	70V3569S4BC Renesas Electronics	1	The 70V3569 is a high-speed 16K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3569 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	BGA	70V3569S4BC	3D model available Symbol and footprint available 3	1 Download Model
	6116LA35DB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Dual-In-Line Packages	6116LA35DB	3D model available Symbol and footprint available 3	1 Download Model
	70V657S12BCGI Renesas Electronics	1	The 70V657 is a high-speed 32K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	BGA	70V657S12BCGI	3D model available Symbol and footprint available 3	1 Download Model
	70T633S12BFI Renesas Electronics	1	The 70T633 is a high-speed 512K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T633S12BFI	3D model available Symbol and footprint available 3	1 Download Model
	70V631S15BF8 Renesas Electronics	1	The 70V631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po	BGA	70V631S15BF8	3D model available Symbol and footprint available 3	1 Download Model

	71V3556SA150BQ8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA150BQ8	3D model available Symbol and footprint available 3	1 Download Model
	M48Z58Y-70MH1F STMicroelectronics	1	5 V, 64 Kbit (8 Kb x 8) ZEROPOWER® SRAM	Small Outline Packages	M48Z58Y-70MH1F	3D model available Symbol and footprint available 3	1 Download Model
	71V67703S85PFGI Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67703S85PFGI	3D model available Symbol and footprint available 3	1 Download Model
	7132LA55PDGI Renesas Electronics	1	The 7132 is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7142 "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535	Dual-In-Line Packages	7132LA55PDGI	3D model available Symbol and footprint available 3	1 Download Model
	71V124SA12YG8 Renesas Electronics	1	The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71V124SA12YG8	3D model available Symbol and footprint available 3	1 Download Model
	71V67903S85PFG Renesas Electronics	1	The 71V67903 3.3V CMOS SRAM is organized as 512K x 18. The 71V67903 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67903S85PFG	3D model available Symbol and footprint available 3	1 Download Model
	7024S70GB Renesas Electronics	1	The 7024 is a high-speed 4Kx 16 Dual-Port Static RAM designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. An automatic power down feature controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7024S70GB	3D model available Symbol and footprint available 3	1 Download Model
	6116SA45DB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Dual-In-Line Packages	6116SA45DB	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA133BG8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA133BG8	3D model available Symbol and footprint available 3	1 Download Model
	RMQS3A1836DGBA-302#AC0 Renesas Electronics	1	The RMQS3A1836DGBA is a 524, 288-word by 36-bit and the RMQS3A1818DGBA is a 1, 048, 576-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed	BGA	RMQS3A1836DGBA-302#AC0	3D model available Symbol and footprint available 3	1 Download Model
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