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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72825LB10PF8 Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB10PF8	3D model available Symbol and footprint available 3	1 Download Model
	C1812H103JBGAE7282 KEMET	1	SMD Indust C0G HVHT200C, Ceramic, 0.01 uF, 5%, 630 VDC, 945 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 100 GOhms, 87 mg, 1812, 4.5mm, 3.2mm, 2.5mm, 0.6mm, 42, 26 Weeks, 120	Other	C1812H103JBGAE7282	3D model available Symbol and footprint available 3	1 Download Model
	C1210H104J5GAF7282 KEMET	1	SMD Indust C0G HT200C, Ceramic, 0.1 uF, 5%, 50 VDC, 125 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 10 GOhms, 40 mg, 1210, 3.2mm, 2.5mm, 1.25mm, 0.5mm, 80, 78 Weeks, 120	Other	C1210H104J5GAF7282	3D model available Symbol and footprint available 3	1 Download Model
	72821L25TF Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L25TF	3D model available Symbol and footprint available 3	1 Download Model

	72825LB15PFGI8 Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	C0603H102F5GAE7282 KEMET	1	SMD Indust C0G HT200C, Ceramic, 1000 pF, 1%, 50 VDC, 125 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 100 GOhms, 3.7 mg, 0603, 1.6mm, 0.8mm, 0.8mm, 0.7mm, 0.35mm, 368, 26 Weeks, 120	Other	C0603H102F5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	72825LB15BGG Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	BGA	72825LB15BGG	3D model available Symbol and footprint available 3	1 Download Model
	C0603H102J5GAE7282 KEMET	1	SMD Indust C0G HT200C, Ceramic, 1000 pF, 5%, 50 VDC, 125 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 100 GOhms, 3.7 mg, 0603, 1.6mm, 0.8mm, 0.8mm, 0.7mm, 0.35mm, 368, 26 Weeks, 120	Other	C0603H102J5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	C0603H222F5GAC7282 KEMET	1	SMD Indust C0G HT200C, Ceramic, 2200 pF, 1%, 50 VDC, 125 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 100 GOhms, 3.7 mg, 0603, 1.6mm, 0.8mm, 0.8mm, 0.7mm, 0.35mm, 368, 78 Weeks, 120	Other	C0603H222F5GAC7282	3D model available Symbol and footprint available 3	1 Download Model
	TCD-17-282X+ Mini-Circuits	1	Signal Conditioning DIR COUP / SURF MT / RoHS	Other	TCD-17-282X+	3D model available Symbol and footprint available 3	1 Download Model
	ADV7282WBCPZ-M-RL Analog Devices	1	Video Decoder 1ADC 10bit Automotive 32-Pin LFCSP EP T/R	Quad Flat No-Lead	ADV7282WBCPZ-M-RL	3D model available Symbol and footprint available 3	1 Download Model
	ADV7282WBCPZ-RL Analog Devices	1	Video Decoder 1ADC 10bit Automotive 32-Pin LFCSP EP T/R	Quad Flat No-Lead	ADV7282WBCPZ-RL	3D model available Symbol and footprint available 3	1 Download Model
	UCC27282DR Texas Instruments	1	Gate Drivers 3-A, 120-V half bridge gate driver with 5-V UVLO, interlock and enable	Small Outline Packages	UCC27282DR	3D model available Symbol and footprint available 3	1 Download Model
	C1812H224J5GAE7282 KEMET	1	SMD Indust C0G HT200C, Ceramic, 0.22 uF, 5%, 50 VDC, 125 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 4.5455 GOhms, 87 mg, 1812, 4.5mm, 3.2mm, 1.6mm, 0.6mm, 42, 26 Weeks, 120	Other	C1812H224J5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	C2220H362JGGAF7282 KEMET	1	SMD Indust C0G HVHT200C, Ceramic, 3600 pF, 5%, 2000 VDC, 2400 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 100 GOhms, 320 mg, 2220, 5.7mm, 5mm, 2.5mm, 0.6mm, 20, 78 Weeks, 120	Other	C2220H362JGGAF7282	3D model available Symbol and footprint available 3	1 Download Model

	DA7282-00V42 Renesas Electronics	1	The DA7282 ultra-low power haptic driver, combines custom drive sequences, on- and off-resonance, at up to 1kHz. The DA7282 drives both ERM and LRA (narrow and wideband) actuators and track resonance up to 300Hz producing highly complex click/vibration touch effects in a wide range of applications.The DA7282 differs from the DA7280 and DA7281 by providing the capability to go into a full standby mode, lowering current consumption to 5nA.Benefitst20x lower standby current, minimizing the drain on small batte	BGA	DA7282-00V42	3D model available Symbol and footprint available 3	1 Download Model
	72821L15TFI8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L15TFI8	3D model available Symbol and footprint available 3	1 Download Model
	C0805H103J5GAF7282 KEMET	1	SMD Indust C0G HT200C, Ceramic, 0.01 uF, 5%, 50 VDC, 125 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 100 GOhms, 11 mg, 0805, 2mm, 1.25mm, 0.78mm, 0.75mm, 0.5mm, 100, 78 Weeks, 120	Other	C0805H103J5GAF7282	3D model available Symbol and footprint available 3	1 Download Model
	7447728215 Würth Elektronik	1	Radial Leaded Wire Wound Inductor WE-TI	Other	7447728215	3D model available Symbol and footprint available 3	1 Download Model
	72825LB10PFG Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB10PFG	3D model available Symbol and footprint available 3	1 Download Model
	1728297 Phoenix Contact	1	PCB terminal block, nominal current: 10 A, rated voltage (III/2): 200 V, nominal cross section: 1 mm?, Number of potentials: 3, Number of rows: 1, Number of positions per row: 3, product range: SMKDS 1, pitch: 3.81 mm, connection method: Screw connection with tension sleeve, mounting: Wave soldering, conductor/PCB connection direction: 35 ?, color: green, Pin layout: Linear pinning, Solder pin [P]: 3.5 mm, type of packaging: packed in cardboard	Other	1728297	3D model available Symbol and footprint available 3	1 Download Model
	72821L25TFI Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L25TFI	3D model available Symbol and footprint available 3	1 Download Model
	DA7282-00V4C Renesas Electronics	1	The DA7282 ultra-low power haptic driver, combines custom drive sequences, on- and off-resonance, at up to 1kHz. The DA7282 drives both ERM and LRA (narrow and wideband) actuators and track resonance up to 300Hz producing highly complex click/vibration touch effects in a wide range of applications.The DA7282 differs from the DA7280 and DA7281 by providing the capability to go into a full standby mode, lowering current consumption to 5nA.Benefitst20x lower standby current, minimizing the drain on small batte	BGA	DA7282-00V4C	3D model available Symbol and footprint available 3	1 Download Model
	72821L10PFG Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72821L15PF8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L15PF8	3D model available Symbol and footprint available 3	1 Download Model
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