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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V851L10PFG Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72225LB10PFG8 Renesas Electronics	1	The 72225 is a 1K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72225LB10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72221L10PFG8 Renesas Electronics	1	The 72221SyncFIFO™ is a 1K x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72221L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L7-5PFGI8 Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model

	723624L15PFG Renesas Electronics	1	The 723624 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 256 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723624L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V211L15PFGI8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V211L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAG Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15TFGI Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TFGI	3D model available Symbol and footprint available 3	1 Download Model
	72615L35PF Renesas Electronics	1	The 72615 is a 512 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Quad Flat Packages	72615L35PF	3D model available Symbol and footprint available 3	1 Download Model
	72T1845L5BB Renesas Electronics	1	The 72T1845 is a 2K x 18 / 4K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1845L5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V281L15TFGI8 Renesas Electronics	1	The 72V281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72281 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V281L15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72T36125L5BBGI Renesas Electronics	1	The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36125L5BBGI	3D model available Symbol and footprint available 3	1 Download Model
	72V845L15PFGI8 Renesas Electronics	1	The 72V845 is a 4K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V245 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V845L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V3640L7-5BB Renesas Electronics	1	The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3640L7-5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V251L10PFG8 Renesas Electronics	1	The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V251L10PFG8	3D model available Symbol and footprint available 3	1 Download Model

	72V3690L7-5BB8 Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V253L7-5PFGI8 Renesas Electronics	1	The 72V253 8K x 9/4K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V253L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	7205L12TPG8 Renesas Electronics	1	The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7205L12TPG8	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAGI Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAGI	3D model available Symbol and footprint available 3	1 Download Model
	72V235L10TFG8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72285L15PFGI8 Renesas Electronics	1	The 72285 is a 64K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72285L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72T18105L6-7BB Renesas Electronics	1	The 72T18105 is a 128K x 18 / 256K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18105L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72413L25SOG8 Renesas Electronics	1	The 72413 is a 64 x 5, high-speed First-In/First-Out memory. It is expandable in bit width. All speed versions are cascadable in depth. It is ideal for use in high-speed data buffering applications. This FIFO can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers and graphics controllers.	Small Outline Packages	72413L25SOG8	3D model available Symbol and footprint available 3	1 Download Model
	72V3670L6PFG Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3670L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V293L7-5BCI Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V293L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model
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