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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V3690L6BBG8 Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L6BBG8	3D model available Symbol and footprint available 3	1 Download Model
	72V223L7-5BCI Renesas Electronics	1	The 72V223 1K x 9/512 x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V223L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model
	72T36105L10BB Renesas Electronics	1	The 72T36105 is a 64K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36105L10BB	3D model available Symbol and footprint available 3	1 Download Model
	7202LA30DB Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7202LA30DB	3D model not available Symbol and footprint available 2	1 Download Model

	72V253L6PFG Renesas Electronics	1	The 72V253 8K x 9/4K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V253L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	7285L15PAGI8 Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L15PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	723622L15PFG Renesas Electronics	1	The 723622 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 256 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723622L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	7205L12PDG Renesas Electronics	1	The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7205L12PDG	3D model available Symbol and footprint available 3	1 Download Model
	72V261LA10TFG8 Renesas Electronics	1	The 72V261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72261 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V261LA10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L6PFG Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3650L7-5BBI Renesas Electronics	1	The 72V3650 2K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3650L7-5BBI	3D model available Symbol and footprint available 3	1 Download Model
	72255LA15PFGI Renesas Electronics	1	The 72255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72255LA15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72831L10PFG8 Renesas Electronics	1	The 72831 is a 2K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations s	Quad Flat Packages	72831L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V235L10PFG8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V03L25JGI Renesas Electronics	1	The 72V03 is a 2K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V03L25JGI	3D model available Symbol and footprint available 3	1 Download Model

	72T1895L4-4BBG Renesas Electronics	1	Asynchronous, Synchronous FIFO 1.125M (64K x 18)(128K x 9) Uni-Directional 100MHz, 225MHz 8ns, 3.4ns 144-PBGA (13x13)	BGA	72T1895L4-4BBG	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7802-60FN Texas Instruments	1	FIFO 1024 X 18 Synch FIFO Memory	Plastic Leaded Chip Carrier	SN74ACT7802-60FN	3D model not available Symbol and footprint available 2	1 Download Model
	IDT72V04L25JGI Renesas Electronics	1	FIFO, 4KX9, 25ns, Asynchronous, CMOS, PQCC32	Plastic Leaded Chip Carrier	IDT72V04L25JGI	3D model available Symbol and footprint available 3	1 Download Model
	72V82L15PAG8 Renesas Electronics	1	FIFO 1K x 9 DualAsync FIFO 3.3V 15ns	Small Outline Packages	72V82L15PAG8	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT3622-30PQ Texas Instruments	1	FIFO 256 x 36 x 2 bidir Synch FIFO Memory	Quad Flat Packages	SN74ACT3622-30PQ	3D model available Symbol and footprint available 3	1 Download Model
	IDT7203L15TPGI Renesas Electronics	1	IDT IDT7203L15TPGI, FIFO Memory, Dual 18kbit, 2K x 9 bit, Bi-Directional 15ns, 4.5 → 5.5 V, 28-Pin PDIP	Dual-In-Line Packages	IDT7203L15TPGI	3D model available Symbol and footprint available 3	1 Download Model
	CD74HCT40105MT Texas Instruments	1	TEXAS INSTRUMENTS - CD74HCT40105MT - FIFO, 15MHZ, SOIC-16	Small Outline Packages	CD74HCT40105MT	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7805-40DLR Texas Instruments	1	FIFO 256 x 18 synchronous FIFO memory	Small Outline Packages	SN74ACT7805-40DLR	3D model available Symbol and footprint available 3	1 Download Model
	SN74V215-15PAG Texas Instruments	1	Texas Instruments SN74V215-15PAG, FIFO Memory, Dual, 512 x 18, Uni-Directional 10ns 66.7MHz, 3 → 3.6 V, 64-Pin	Quad Flat Packages	SN74V215-15PAG	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT2235-60PAG Texas Instruments	1	FIFO 1024x9x2 Asynch Bidir FIFO Mem	Quad Flat Packages	SN74ACT2235-60PAG	3D model available Symbol and footprint available 3	1 Download Model
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