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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	723651L15PFG Renesas Electronics	1	The 723651 is a 2K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723651L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	72841L10TFG Renesas Electronics	1	The 72841 is a 4K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72241 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72841 architecture lends itself to many flexible configurations s	Quad Flat Packages	72841L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3640L7-5BB8 Renesas Electronics	1	The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3640L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V263L6BC Renesas Electronics	1	The 72V263 16K x 9/8K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V263L6BC	3D model available Symbol and footprint available 3	1 Download Model

	72T1845L6-7BB Renesas Electronics	1	The 72T1845 is a 2K x 18 / 4K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1845L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72V205L15PFGI8 Renesas Electronics	1	The 72V205 is a 256 x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V205L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	7207L30DB Renesas Electronics	1	The 7207 is a 32K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7207L30DB	3D model not available Symbol and footprint available 2	1 Download Model
	72240L10TPG Renesas Electronics	1	The 72240 is a 4K x 8 SyncFIFO™ with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication. It has 8-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Dual-In-Line Packages	72240L10TPG	3D model available Symbol and footprint available 3	1 Download Model
	7202LA20TDB Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7202LA20TDB	3D model not available Symbol and footprint available 2	1 Download Model
	72245LB10PFG8 Renesas Electronics	1	The 72245 is a 4K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72245LB10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	7201LA15JGI8 Renesas Electronics	1	The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7201LA15JGI8	3D model not available Symbol and footprint available 2	1 Download Model
	72V3680L6BB Renesas Electronics	1	The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3680L6BB	3D model available Symbol and footprint available 3	1 Download Model
	72T18125L4-4BBG Renesas Electronics	1	The 72T18125 is a 512K x 18 / 1M x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18125L4-4BBG	3D model available Symbol and footprint available 3	1 Download Model
	72V243L7-5PFGI8 Renesas Electronics	1	The 72V243 4K x 9/2K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V243L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72605L50J Renesas Electronics	1	The 72605 is a 256 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Plastic Leaded Chip Carrier	72605L50J	3D model not available Symbol and footprint available 2	1 Download Model

	7281L12PAG Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L12PAG	3D model available Symbol and footprint available 3	1 Download Model
	72V211L10PFG8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V211L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V201L10PFG Renesas Electronics	1	The 72V201 is a 256 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72201 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V201L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T36115L4-4BBG Renesas Electronics	1	The 72T36115 is a 128K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36115L4-4BBG	3D model available Symbol and footprint available 3	1 Download Model
	72241L10PFG8 Renesas Electronics	1	The 72241SyncFIFO™ is a 4K x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72241L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	723651L15PFG8 Renesas Electronics	1	The 723651 is a 2K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723651L15PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72211L10JG8 Renesas Electronics	1	The 72211SyncFIFO™ is a 512 x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Plastic Leaded Chip Carrier	72211L10JG8	3D model not available Symbol and footprint available 2	1 Download Model
	72V801L15PFGI Renesas Electronics	1	The 72V801is a 256 x 9 dual synchronous FIFO that is functionally equivalent to two 72V201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V801L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V225L10PFG8 Renesas Electronics	1	The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V225L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V3622L10PFG8 Renesas Electronics	1	The 72V3622 is a 3.3V version of the 723622. Two independent 256 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	72V3622L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
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