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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	7205L12TPG Renesas Electronics	1	The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7205L12TPG	3D model available Symbol and footprint available 3	1 Download Model
	72V2101L10PFG8 Renesas Electronics	1	The 72V2101 is a 256K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Supe	Quad Flat Packages	72V2101L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V263L6PFG Renesas Electronics	1	The 72V263 16K x 9/8K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V263L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72615L25J Renesas Electronics	1	The 72615 is a 512 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Plastic Leaded Chip Carrier	72615L25J	3D model not available Symbol and footprint available 2	1 Download Model

	72V245L15PFGI Renesas Electronics	1	The 72V245 is a 4K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72245 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V245L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72245LB10JG Renesas Electronics	1	The 72245 is a 4K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Plastic Leaded Chip Carrier	72245LB10JG	3D model available Symbol and footprint available 3	1 Download Model
	72V243L7-5BCI Renesas Electronics	1	The 72V243 4K x 9/2K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V243L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model
	72225LB10PFG Renesas Electronics	1	The 72225 is a 1K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72225LB10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V215L10TFG8 Renesas Electronics	1	The 72V215 is a 512 x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72215 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V215L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V265LA15PFGI Renesas Electronics	1	The 72V265 is an 16K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72265 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V265LA15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V255LA10PFG8 Renesas Electronics	1	The 72V255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72255 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that nee	Quad Flat Packages	72V255LA10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72225LB15PFGI8 Renesas Electronics	1	The 72225 is a 1K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72225LB15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V3672L10PFG8 Renesas Electronics	1	The 72V3672 Bidirectional SyncFIFO (clocked) memory is a 3.3V version of the 723672. Two independent 8K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	72V3672L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V281L15PFGI Renesas Electronics	1	The 72V281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72281 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V281L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V36110L7-5BBGI8 Renesas Electronics	1	The 72V36110 128K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V36110L7-5BBGI8	3D model available Symbol and footprint available 3	1 Download Model

	72V36100L6BBG Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V36100L6BBG	3D model available Symbol and footprint available 3	1 Download Model
	72T1885L6-7BB Renesas Electronics	1	The 72T1885 is a 32K x 18 / 64K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1885L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	CD40105BKMSR Renesas Electronics	1	CD40105BMS is a low-power first-in-first-out (FIFO) elastic storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A 1 signifies that the position's data is filled and a 0 denotes a vacancy in that position. The control flip-flop detects the state of the preced	Small Outline Packages	CD40105BKMSR	3D model available Symbol and footprint available 3	1 Download Model
	72V223L7-5BC Renesas Electronics	1	The 72V223 1K x 9/512 x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V223L7-5BC	3D model available Symbol and footprint available 3	1 Download Model
	72V201L15PFGI8 Renesas Electronics	1	The 72V201 is a 256 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72201 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V201L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V801L10PFG Renesas Electronics	1	The 72V801is a 256 x 9 dual synchronous FIFO that is functionally equivalent to two 72V201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V801L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	723631L20PFGI Renesas Electronics	1	The 723631 is a 512 x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723631L20PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V2103L7-5BC Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V2103L7-5BC	3D model available Symbol and footprint available 3	1 Download Model
	72T36125L6-7BB Renesas Electronics	1	The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36125L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72V2101L10PFG Renesas Electronics	1	The 72V2101 is a 256K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Supe	Quad Flat Packages	72V2101L10PFG	3D model available Symbol and footprint available 3	1 Download Model
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