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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V05L25JGI8 Renesas Electronics	1	The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V05L25JGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V211L15PFGI Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V211L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V273L10PFG Renesas Electronics	1	The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V273L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T18125L5BB Renesas Electronics	1	The 72T18125 is a 512K x 18 / 1M x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18125L5BB	3D model available Symbol and footprint available 3	1 Download Model

	72281L10PFG Renesas Electronics	1	The 72281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperS	Quad Flat Packages	72281L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V84L15PAG Renesas Electronics	1	The 72V84 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V84L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	72V3640L6BB8 Renesas Electronics	1	The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3640L6BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V3670L6BB8 Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3670L6BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L6BBG Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L6BBG	3D model available Symbol and footprint available 3	1 Download Model
	72221L10PFG Renesas Electronics	1	The 72221SyncFIFO™ is a 1K x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72221L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72265LA10PFG Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V223L6BC Renesas Electronics	1	The 72V223 1K x 9/512 x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V223L6BC	3D model available Symbol and footprint available 3	1 Download Model
	72801L10PFG8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72T1875L6-7BB Renesas Electronics	1	The 72T1875 is a 16K x 18 / 32K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1875L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72285L10PFG Renesas Electronics	1	The 72285 is a 64K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72285L10PFG	3D model available Symbol and footprint available 3	1 Download Model

	72V3623L10PFG8 Renesas Electronics	1	The 72V3623 is a 256 x 36 Sync FIFO that is a 3.3V version of the 723623. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. These devices can operate in the IDT Standard mode word or First Word Fall Through mode.	Quad Flat Packages	72V3623L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72T36115L6-7BB Renesas Electronics	1	The 72T36115 is a 128K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36115L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72V285L10PFG Renesas Electronics	1	The 72V285 is an 64K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72285 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V285L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3632L10PFG Renesas Electronics	1	The 72V3632 is a 3.3V version of the 723632. Two independent 512 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	72V3632L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	7207L20JGI Renesas Electronics	1	The 7207 is a 32K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7207L20JGI	3D model not available Symbol and footprint available 2	1 Download Model
	72V285L10PFG8 Renesas Electronics	1	The 72V285 is an 64K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72285 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V285L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	723651L15PF Renesas Electronics	1	The 723651 is a 2K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723651L15PF	3D model available Symbol and footprint available 3	1 Download Model
	72V273L6PFG Renesas Electronics	1	The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V273L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	7206L20DB Renesas Electronics	1	The 7206 is a 16K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7206L20DB	3D model not available Symbol and footprint available 2	1 Download Model
	72V225L10TFG Renesas Electronics	1	The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V225L10TFG	3D model available Symbol and footprint available 3	1 Download Model
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