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236-7 Model Download Search Results

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Image Part Number D.S Description Package Category Prices / Stock Model Action
Image Part Number D.S Description Package Category Prices / Stock Model Action
Part Image Part Image
2367196-6 TE Connectivity
1 PCB Mount Header, Right Angle, Wire-to-Board, 6 Position, 1 mm [.039 in] Centerline, Fully Shrouded, Tin, Surface Mount, Signal, Black Other 2367196-6 1 Download Model
Part Image Part Image 1 High Speed Optocouplers Hi Spd Logic Output photocoupler; 5-pin SO6; RoHS; Other TLP2367(V4-TPL,E 1 Download Model
Part Image Part Image
2367196-5 TE Connectivity
1 PCB Mount Header, Right Angle, Wire-to-Board, 5 Position, 1 mm [.039 in] Centerline, Fully Shrouded, Tin, Surface Mount, Signal, Black, Tape & Reel Other 2367196-5 1 Download Model
Part Image Part Image
1822367 Phoenix Contact
1 PCB terminal block, nominal current: 13.5 A, rated voltage (III/2): 160 V, nominal cross section: 1.5 mm?, Number of potentials: 7, Number of rows: 1, Number of positions per row: 7, product range: SPT 1,5/..-V-THR, pitch: 3.5 mm, connection method: Push-in spring connection, mounting: THR soldering, conductor/PCB connection direction: 90 ?, color: black, Pin layout: Linear double pinning, Solder pin [P]: 2.6 mm, type of packaging: packed in cardboard Other 1822367 1 Download Model
Part Image Part Image
2367196-3 TE Connectivity
1 Body Features: Primary Product Color Black | Configuration Features: PCB Mount Orientation Right Angle | Number of Rows 1 | Number of Positions 3 | Contact Features: Contact Mating Area Plating Material Thickness 50 MICIN | Contact Current Rating (Max) 2 AMP | Contact Mating Area Plating Material Finish Matte | Contact Mating Area Plating Material Tin | Contact Mating Area Plating Material Thickness 1.27 MICM | Contact Type Pin | Electrical Characteristics: Operating Voltage 50 VAC | Housing Features: Housi Other 2367196-3 1 Download Model
Part Image Part Image
723676L12PF8 Renesas Electronics
1 The 723676 is a 8K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode. Quad Flat Packages 723676L12PF8 1 Download Model
Part Image Part Image
723672L12PF Renesas Electronics
1 The 723672 is a Bidirectional SyncFIFO (clocked) memory. Two independent 8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723672L12PF 1 Download Model
Part Image Part Image
2367197-8 TE Connectivity
1 Body Features: Primary Product Color Black | Configuration Features: Number of Rows 1 | Number of Positions 8 | PCB Mount Orientation Vertical | Contact Features: Contact Mating Area Plating Material Thickness 1.27 MICM | Contact Current Rating (Max) 2 AMP | Contact Mating Area Plating Material Finish Matte | Contact Type Pin | Contact Mating Area Plating Material Thickness 50 MICIN | Contact Mating Area Plating Material Tin | Electrical Characteristics: Operating Voltage 50 VAC | Housing Features: Centerli Other 2367197-8 1 Download Model
Part Image Part Image
2367197-6 TE Connectivity
1 1.0mm WTB Side Vertical Type With Latch,Connector Header Surface Mount 6 position 0.039" (1.00mm) Other 2367197-6 1 Download Model
Part Image Part Image
LTC2367CMS-16#PBF Analog Devices
1 Analog to Digital Converters - ADC 16-Bit, 500ksps, Pseudo-Differential Unipolar SAR ADC with 94.7dB SNR Small Outline Packages LTC2367CMS-16#PBF 1 Download Model
Part Image Part Image 1 Vishay SI2367DS-T1-GE3 P-channel MOSFET Transistor, 2.2 A, -20 V, 3-Pin TO-236 SOT23 (3-Pin) SI2367DS-T1-GE3 1 Download Model
Part Image Part Image
1622367-1 TE Connectivity
1 TE Connectivity LR1 Series Through Hole Thin Film Resistor 1MΩ ±1% 0.6W ±50ppm/°C Resistors, Axial Diameter Horizontal Mounting 1622367-1 1 Download Model
Part Image Part Image
2367197-4 TE Connectivity
1 1.0mm WTB Side Vertical Type With Latch Other 2367197-4 1 Download Model
Part Image Part Image
2367196-8 TE Connectivity
1 Body Features: Primary Product Color Black | Configuration Features: PCB Mount Orientation Right Angle | Number of Rows 1 | Number of Positions 8 | Contact Features: Contact Mating Area Plating Material Thickness 1.27 MICM | Contact Current Rating (Max) 2 AMP | Contact Type Pin | Contact Mating Area Plating Material Finish Matte | Contact Mating Area Plating Material Tin | Contact Mating Area Plating Material Thickness 50 MICIN | Electrical Characteristics: Operating Voltage 50 VAC | Housing Features: Cente Other 2367196-8 1 Download Model
Part Image Part Image
723673L12PF8 Renesas Electronics
1 The 723673 is a 8K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. This device can operate in the IDT Standard mode Quad Flat Packages 723673L12PF8 1 Download Model
Part Image Part Image
723672L12PF8 Renesas Electronics
1 The 723672 is a Bidirectional SyncFIFO (clocked) memory. Two independent 8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723672L12PF8 1 Download Model
Part Image Part Image
723672L15PF Renesas Electronics
1 The 723672 is a Bidirectional SyncFIFO (clocked) memory. Two independent 8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723672L15PF 1 Download Model
Part Image Part Image
DF2367VF33V Renesas Electronics
1 The H8S/2368 Group is supported only for customers who have already adopted these products. The RX651 Group is recommended for new designs. Quad Flat Packages DF2367VF33V 1 Download Model
Part Image Part Image
1-2367197-0 TE Connectivity
1 1.0mm WTB Side Vertical Type With Latch Other 1-2367197-0 1 Download Model
Part Image Part Image
1-2367196-0 TE Connectivity
1 1.0mm WTB RIGHT ANGLE TYPE WITH LATCH Other 1-2367196-0 1 Download Model
Part Image Part Image
723676L12PF Renesas Electronics
1 The 723676 is a 8K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode. Quad Flat Packages 723676L12PF 1 Download Model
Part Image Part Image
723673L12PF Renesas Electronics
1 The 723673 is a 8K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. This device can operate in the IDT Standard mode Quad Flat Packages 723673L12PF 1 Download Model
Part Image Part Image
723676L15PF Renesas Electronics
1 The 723676 is a 8K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode. Quad Flat Packages 723676L15PF 1 Download Model
Part Image Part Image
1823670 Phoenix Contact
1 PCB terminal block, nominal current: 13.5 A, rated voltage (III/2): 160 V, nominal cross section: 1.5 mm?, Number of potentials: 6, Number of rows: 1, Number of positions per row: 6, product range: SPT 1,5/..-H-THR, pitch: 3.5 mm, connection method: Push-in spring connection, mounting: THR soldering, conductor/PCB connection direction: 0 ?, color: black, Pin layout: Linear double pinning, Solder pin [P]: 2 mm, type of packaging: 44 mm wide tape Other 1823670 1 Download Model
Part Image Part Image
723672L15PF8 Renesas Electronics
1 The 723672 is a Bidirectional SyncFIFO (clocked) memory. Two independent 8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723672L15PF8 1 Download Model
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