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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71256SA12YG Renesas Electronics	1	The 71256SA 5V CMOS SRAM is organized as 32K x 8. All bidirectional inputs and outputs of the 71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71256SA12YG	3D model available Symbol and footprint available 3	1 Download Model
	70T651S12BC Renesas Electronics	1	The 70T651 is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T651S12BC	3D model available Symbol and footprint available 3	1 Download Model
	70V657S10BC Renesas Electronics	1	The 70V657 is a high-speed 32K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	BGA	70V657S10BC	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S100BQ Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S100BQ	3D model available Symbol and footprint available 3	1 Download Model

	7026L35GB Renesas Electronics	1	The 7026 is a high-speed 16K x 16 Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7026L35GB	3D model available Symbol and footprint available 3	1 Download Model
	7005L35GB Renesas Electronics	1	The 7005 is a high-speed 8K x 8 Dual-Port Static RAM designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7005L35GB	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S133BGGI8 Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S133BGGI8	3D model available Symbol and footprint available 3	1 Download Model
	70V3319S166BF Renesas Electronics	1	The 70V3319 is a high-speed 256K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3319 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	BGA	70V3319S166BF	3D model available Symbol and footprint available 3	1 Download Model
	71V65703S85BQ Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65703S85BQ	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA166BGG Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA166BGG	3D model available Symbol and footprint available 3	1 Download Model
	70V26L25G Renesas Electronics	1	The 70V26 is a high-speed 16K x 16 Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or wider memory system applications resulting in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Other	70V26L25G	3D model available Symbol and footprint available 3	1 Download Model
	70P249L65BYGI Renesas Electronics	1	The IDT70P249 is a very low power 4K x 16 Dual-Port Static RAM. The IDT70P249 is designed to be used as a stand-alone 64K-bit Dual-Port SRAM. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CS permits the on-chip circuitry of each port to enter a very low standby power mode.Fabricated using Renesas' CMOS high-performance technology,	BGA	70P249L65BYGI	3D model available Symbol and footprint available 3	1 Download Model
	70T3339S166BC Renesas Electronics	1	The 70T3339 is a high-speed 512K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3339 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3339S166BC	3D model available Symbol and footprint available 3	1 Download Model
	71V67703S75PFG8 Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67703S75PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71016S20PHG Renesas Electronics	1	The 71016 5V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71016 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Small Outline Packages	71016S20PHG	3D model available Symbol and footprint available 3	1 Download Model

	71V3556SA100BQG Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA100BQG	3D model available Symbol and footprint available 3	1 Download Model
	70V7319S166BC Renesas Electronics	1	The 70V7319 is a high-speed 256K x 18 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4K x 18 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4K x 18 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7319S166BC	3D model available Symbol and footprint available 3	1 Download Model
	R1LV1616HBG-4SI#B0 Renesas Electronics	1	The R1LV1616HBG-I Series is 16-Mbit static RAM organized 1-Mword × 16-bit with embedded ECC. R1LV1616HBG-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48-ball plastic FBGA for high density surface mounting.	BGA	R1LV1616HBG-4SI#B0	3D model available Symbol and footprint available 3	1 Download Model
	7133LA20JG Renesas Electronics	1	The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available.	Plastic Leaded Chip Carrier	7133LA20JG	3D model available Symbol and footprint available 3	1 Download Model
	71V3577S80BGGI8 Renesas Electronics	1	The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V3577S80BGGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S133PFGI8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65603S133PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	7005L20PFGI Renesas Electronics	1	The 7005 is a high-speed 8K x 8 Dual-Port Static RAM designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Quad Flat Packages	7005L20PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V35761SA183BG Renesas Electronics	1	The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM.	BGA	71V35761SA183BG	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA166BQGI8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA166BQGI8	3D model available Symbol and footprint available 3	1 Download Model
	71T75602S133PFGI8 Renesas Electronics	1	The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75602 contains data I/O, address and control signal registers.	Quad Flat Packages	71T75602S133PFGI8	3D model available Symbol and footprint available 3	1 Download Model
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