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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	7281L15PAGI Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAGI	3D model available Symbol and footprint available 3	1 Download Model
	7285L15PAGI8 Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L15PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V3650L7-5BBI Renesas Electronics	1	The 72V3650 2K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3650L7-5BBI	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAG Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAG	3D model available Symbol and footprint available 3	1 Download Model

	72281L10PFG8 Renesas Electronics	1	The 72281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperS	Quad Flat Packages	72281L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72615L35PF Renesas Electronics	1	The 72615 is a 512 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Quad Flat Packages	72615L35PF	3D model available Symbol and footprint available 3	1 Download Model
	7284L15PAGI Renesas Electronics	1	The 7284 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7284L15PAGI	3D model available Symbol and footprint available 3	1 Download Model
	7205L12TPG8 Renesas Electronics	1	The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7205L12TPG8	3D model available Symbol and footprint available 3	1 Download Model
	7200L15SOGI8 Renesas Electronics	1	The 7200 is a 256 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7200L15SOGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L6PFG Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3670L6PFG Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3670L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	7202LA15JGI Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7202LA15JGI	3D model not available Symbol and footprint available 2	1 Download Model
	72T18105L6-7BB Renesas Electronics	1	The 72T18105 is a 128K x 18 / 256K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18105L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72413L25SOG8 Renesas Electronics	1	The 72413 is a 64 x 5, high-speed First-In/First-Out memory. It is expandable in bit width. All speed versions are cascadable in depth. It is ideal for use in high-speed data buffering applications. This FIFO can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers and graphics controllers.	Small Outline Packages	72413L25SOG8	3D model available Symbol and footprint available 3	1 Download Model
	72831L10PFG8 Renesas Electronics	1	The 72831 is a 2K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations s	Quad Flat Packages	72831L10PFG8	3D model available Symbol and footprint available 3	1 Download Model

	72V235L10PFG8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V03L25JGI Renesas Electronics	1	The 72V03 is a 2K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V03L25JGI	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT2228DW Texas Instruments	1	FIFO Dual 256x1 FIFO Mem	Small Outline Packages	SN74ACT2228DW	3D model available Symbol and footprint available 3	1 Download Model
	72T1895L4-4BBG Renesas Electronics	1	Asynchronous, Synchronous FIFO 1.125M (64K x 18)(128K x 9) Uni-Directional 100MHz, 225MHz 8ns, 3.4ns 144-PBGA (13x13)	BGA	72T1895L4-4BBG	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7805-40DLR Texas Instruments	1	FIFO 256 x 18 synchronous FIFO memory	Small Outline Packages	SN74ACT7805-40DLR	3D model available Symbol and footprint available 3	1 Download Model
	CD74HCT40105MT Texas Instruments	1	TEXAS INSTRUMENTS - CD74HCT40105MT - FIFO, 15MHZ, SOIC-16	Small Outline Packages	CD74HCT40105MT	3D model available Symbol and footprint available 3	1 Download Model
	72V82L15PAG8 Renesas Electronics	1	FIFO 1K x 9 DualAsync FIFO 3.3V 15ns	Small Outline Packages	72V82L15PAG8	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7802-60FN Texas Instruments	1	FIFO 1024 X 18 Synch FIFO Memory	Plastic Leaded Chip Carrier	SN74ACT7802-60FN	3D model not available Symbol and footprint available 2	1 Download Model
	SN74ACT3622-30PQ Texas Instruments	1	FIFO 256 x 36 x 2 bidir Synch FIFO Memory	Quad Flat Packages	SN74ACT3622-30PQ	3D model available Symbol and footprint available 3	1 Download Model
	SN74V293PZAEP Texas Instruments	1	Enhanced Product 65536 X 18 Synchronous Fifo Memory	Quad Flat Packages	SN74V293PZAEP	3D model available Symbol and footprint available 3	1 Download Model
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