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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V253L7-5PFGI8 Renesas Electronics	1	The 72V253 8K x 9/4K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V253L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V261LA10TFG8 Renesas Electronics	1	The 72V261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72261 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V261LA10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V211L15PFGI8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V211L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	7284L15PAGI Renesas Electronics	1	The 7284 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7284L15PAGI	3D model available Symbol and footprint available 3	1 Download Model

	72V235L10TFG8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V293L7-5BCI Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V293L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model
	72255LA15PFGI Renesas Electronics	1	The 72255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72255LA15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L6BBG8 Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L6BBG8	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAGI Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAGI	3D model available Symbol and footprint available 3	1 Download Model
	72285L15PFGI8 Renesas Electronics	1	The 72285 is a 64K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72285L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15TFGI Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TFGI	3D model available Symbol and footprint available 3	1 Download Model
	72T18105L6-7BB Renesas Electronics	1	The 72T18105 is a 128K x 18 / 256K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18105L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72V3670L6PFG Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3670L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72413L25SOG8 Renesas Electronics	1	The 72413 is a 64 x 5, high-speed First-In/First-Out memory. It is expandable in bit width. All speed versions are cascadable in depth. It is ideal for use in high-speed data buffering applications. This FIFO can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers and graphics controllers.	Small Outline Packages	72413L25SOG8	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L6PFG Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L6PFG	3D model available Symbol and footprint available 3	1 Download Model

	72V235L10PFG8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V03L25JGI Renesas Electronics	1	The 72V03 is a 2K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V03L25JGI	3D model available Symbol and footprint available 3	1 Download Model
	IDT7201LA15JGI Renesas Electronics	1	IDT IDT7201LA15JGI, FIFO Memory, Dual 4kbit, 512 x 9 bit, Bi-Directional 15ns, 4.5 → 5.5 V, 32-Pin PLCC	Plastic Leaded Chip Carrier	IDT7201LA15JGI	3D model not available Symbol and footprint available 2	1 Download Model
	CD74HCT40105M96 Texas Instruments	1	Texas Instruments CD74HCT40105M96, FIFO Memory 32MHz, 4.5 → 5.5 V, 16-Pin SOIC	Small Outline Packages	CD74HCT40105M96	3D model available Symbol and footprint available 3	1 Download Model
	IDT7204L12JG Renesas Electronics	1	IDT IDT7204L12JG, FIFO Memory, Dual 36kbit, 4K x 9 bit, Bi-Directional 12ns, 4.5 → 5.5 V, 32-Pin PLCC	Plastic Leaded Chip Carrier	IDT7204L12JG	3D model not available Symbol and footprint available 2	1 Download Model
	IDT7202LA15JGI Renesas Electronics	1	IDT IDT7202LA15JGI, FIFO Memory, Dual 9kbit, 1K x 9 bit, Bi-Directional 15ns, 4.5 → 5.5 V, 32-Pin PLCC	Plastic Leaded Chip Carrier	IDT7202LA15JGI	3D model not available Symbol and footprint available 2	1 Download Model
	IDT7203L12TPG Renesas Electronics	1	IDT IDT7203L12TPG, FIFO Memory, Dual 18kbit, 2K x 9 bit, Bi-Directional 12ns, 4.5 → 5.5 V, 28-Pin PDIP	Dual-In-Line Packages	IDT7203L12TPG	3D model available Symbol and footprint available 3	1 Download Model
	IDT7202LA12SOG Renesas Electronics	1	IDT IDT7202LA12SOG, FIFO Memory, Dual 9kbit, 1K x 9 bit, Bi-Directional 12ns, 4.5 → 5.5 V, 28-Pin SOIC	Small Outline Packages	IDT7202LA12SOG	3D model available Symbol and footprint available 3	1 Download Model
	SN74V273-7PZA Texas Instruments	1	FIFO 16384 x 18 Synch FIFO Memory	Quad Flat Packages	SN74V273-7PZA	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7805-15DL Texas Instruments	1	FIFO 256 x 18 synchronous FIFO memory	Small Outline Packages	SN74ACT7805-15DL	3D model available Symbol and footprint available 3	1 Download Model
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