Other Footprint, Symbol and 3D Model search results

Showing 25 of 33685 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72T1845L5BB Renesas Electronics	1	The 72T1845 is a 2K x 18 / 4K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1845L5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L7-5PFGI8 Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V211L15PFGI8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V211L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L7-5BB8 Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model

	72V281L15TFGI8 Renesas Electronics	1	The 72V281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72281 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V281L15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V251L10PFG8 Renesas Electronics	1	The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V251L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72255LA15PFGI Renesas Electronics	1	The 72255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72255LA15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V235L10TFG8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V293L7-5BCI Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V293L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model
	72V253L6PFG Renesas Electronics	1	The 72V253 8K x 9/4K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V253L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T36105L10BB Renesas Electronics	1	The 72T36105 is a 64K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36105L10BB	3D model available Symbol and footprint available 3	1 Download Model
	72285L15PFGI8 Renesas Electronics	1	The 72285 is a 64K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72285L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15TFGI Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L6PFG Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	7202LA15JGI Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7202LA15JGI	3D model not available Symbol and footprint available 2	1 Download Model

	72T18105L6-7BB Renesas Electronics	1	The 72T18105 is a 128K x 18 / 256K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18105L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72V235L10PFG8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7805-40DLR Texas Instruments	1	FIFO 256 x 18 synchronous FIFO memory	Small Outline Packages	SN74ACT7805-40DLR	3D model available Symbol and footprint available 3	1 Download Model
	72T1895L4-4BBG Renesas Electronics	1	Asynchronous, Synchronous FIFO 1.125M (64K x 18)(128K x 9) Uni-Directional 100MHz, 225MHz 8ns, 3.4ns 144-PBGA (13x13)	BGA	72T1895L4-4BBG	3D model available Symbol and footprint available 3	1 Download Model
	IDT7203L15TPGI Renesas Electronics	1	IDT IDT7203L15TPGI, FIFO Memory, Dual 18kbit, 2K x 9 bit, Bi-Directional 15ns, 4.5 → 5.5 V, 28-Pin PDIP	Dual-In-Line Packages	IDT7203L15TPGI	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7802-60FN Texas Instruments	1	FIFO 1024 X 18 Synch FIFO Memory	Plastic Leaded Chip Carrier	SN74ACT7802-60FN	3D model not available Symbol and footprint available 2	1 Download Model
	IDT72V04L25JGI Renesas Electronics	1	FIFO, 4KX9, 25ns, Asynchronous, CMOS, PQCC32	Plastic Leaded Chip Carrier	IDT72V04L25JGI	3D model available Symbol and footprint available 3	1 Download Model
	CD74HCT40105MT Texas Instruments	1	TEXAS INSTRUMENTS - CD74HCT40105MT - FIFO, 15MHZ, SOIC-16	Small Outline Packages	CD74HCT40105MT	3D model available Symbol and footprint available 3	1 Download Model
	72V3640L6BBG Renesas Electronics	1	FIFO 1K x 36 SuperSync II FIFO, 3.3V	BGA	72V3640L6BBG	3D model available Symbol and footprint available 3	1 Download Model
	IDT72V04L15JG Renesas Electronics	1	IDT IDT72V04L15JG, FIFO Memory, Dual 36kbit, 4K x 9 bit, Bi-Directional 15ns, 3 → 3.6 V, 32-Pin PLCC	Plastic Leaded Chip Carrier	IDT72V04L15JG	3D model available Symbol and footprint available 3	1 Download Model
1 2 3 4 5 6 7 8 9

Can't find what you're looking for? Request this part

Other Model Download Search Results

Popular FIFOs