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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	V24C8E100BG3 VICOR	1	Isolated DC/DC Converters E 18/36/24 8v/ 12.5A	Other	V24C8E100BG3	3D model available Symbol and footprint available 3	1 Download Model
	V28C12T100BG3 VICOR	1	Isolated DC/DC Converters Micro Family-Vin-28, Vout-12, Power-100	Other	V28C12T100BG3	3D model available Symbol and footprint available 3	1 Download Model
	V72C5M100BG VICOR	1	Isolated DC/DC Converters - Through Hole Watts- 100 Vin 72 Vout 5 Grade - M	Other	V72C5M100BG	3D model available Symbol and footprint available 3	1 Download Model
	V110C24T100BG VICOR	1	DC DC CONVERTER 24V 100W	Other	V110C24T100BG	3D model available Symbol and footprint available 3	1 Download Model

	FIDO2100BGA128IR0 Analog Devices	1	Ethernet ICs FSA0AA025AB - 3-port Ind Ethernet Switch	BGA	FIDO2100BGA128IR0	3D model available Symbol and footprint available 3	1 Download Model
	V110C48T100BG3 VICOR	1	Isolated Module DC DC Converter 1 Output 48V 2.08A 66V - 154V Input	Other	V110C48T100BG3	3D model available Symbol and footprint available 3	1 Download Model
	V300C5C100BG VICOR	1	Isolated DC/DC Converters Micro Family Vin-300 Vout-5, Power-100	Other	V300C5C100BG	3D model available Symbol and footprint available 3	1 Download Model
	V24C28T100BG VICOR	1	Isolated DC/DC Converters T18 36 24 28.0V3.6A	Other	V24C28T100BG	3D model available Symbol and footprint available 3	1 Download Model
	RS6G100BGTB1 ROHM Semiconductor	1	N-Channel 40 V 100A (Tc) 3W (Ta), 59W (Tc) Surface Mount 8-HSOP	Other	RS6G100BGTB1	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S100BG8 Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2546S100BG8	3D model available Symbol and footprint available 3	1 Download Model
	71T75602S100BGI Renesas Electronics	1	The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75602 contains data I/O, address and control signal registers.	BGA	71T75602S100BGI	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S100BGI Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S100BGI	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA100BG Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA100BG	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S100BGGI Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S100BGGI	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S100BG Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2546S100BG	3D model available Symbol and footprint available 3	1 Download Model

	71V3556SA100BGGI Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA100BGGI	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S100BGI8 Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2546S100BGI8	3D model available Symbol and footprint available 3	1 Download Model
	V24C8H100BG3 VICOR This part was updated within the past 30 days. Set alerts for model updates on the part download page.	1	Isolated DC/DC Converters - Through Hole H 18/36/24 8v/ 12.5A	Other	V24C8H100BG3	3D model available Symbol and footprint available 3	1 Download Model
	R5F100BGDNA#U0 Renesas Electronics	1	The RL78/G13 microcontrollers balance the industry's lowest level of consumption current (CPU: 66 μA/MHz, standby (STOP): 230 nA) and a high performance of 43.2 DMIPS (32 MHz). They have an on-chip oscillator, data flash, A/D converter, and more. Built-in safety features (function that detects illegal operation of hardware) enable support for the household appliance safety standard (IEC/UL 60730). These microcontrollers can be used in a wide variety of applications from home and consumer appliances to indus	Quad Flat No-Lead	R5F100BGDNA#U0	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA100BG Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BG	3D model available Symbol and footprint available 3	1 Download Model
	V28C15T100BG2 VICOR	1	Isolated DC/DC Converters T 9/36/28 15v/ 6.67A	Other	V28C15T100BG2	3D model not available Symbol and footprint available 2	1 Download Model
	70V5388S100BG Renesas Electronics	1	The 70V5388 is a high-speed 64Kx18 bit synchronous FourPort RAM that allows simultaneous access of any address from all four ports and is optimized for applications having unidirectional or bi-directional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. It provides a wide range of functions specially designed to facilitate system operations.	BGA	70V5388S100BG	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA100BGI Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BGI	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA100BG8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BG8	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA100BGI Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA100BGI	3D model available Symbol and footprint available 3	1 Download Model
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