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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	2308-6211-TP 3M	1	Headers & Wire Housings PINSTRIP HDR 08CNT LEN .318" TAIL .120"	Other	2308-6211-TP	3D model available Symbol and footprint available 3	1 Download Model
	2308-2-00-80-00-00-07-0 Mill-Max	1	Terminal Turret Connector Single End 0.156" (3.96mm) Tin	Other	2308-2-00-80-00-00-07-0	3D model available Symbol and footprint available 3	1 Download Model
	2308-6111-TB 3M	1	Conn Unshrouded Header HDR 8 POS 2.54mm Solder ST Top Entry Thru-Hole	Header, Vertical	2308-6111-TB	3D model available Symbol and footprint available 3	1 Download Model
	2308-2-00-44-00-00-07-0 Mill-Max	1	Circuit Board Hardware - PCB 300u AG OVER CU Terminal Turret Connector Single 300 μ" Silver over - 55/+125° C	Other	2308-2-00-44-00-00-07-0	3D model available Symbol and footprint available 3	1 Download Model

	2308-5HDCGI Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-5HDCGI	3D model available Symbol and footprint available 3	1 Download Model
	2308-1HDCGI8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308-5HPGG Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-5HPGG	3D model available Symbol and footprint available 3	1 Download Model
	2308-5HDCGI8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-5HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308-1HPGGI Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1HPGGI	3D model available Symbol and footprint available 3	1 Download Model
	2308-5HDCG8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-5HDCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308-5HDCG Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-5HDCG	3D model available Symbol and footprint available 3	1 Download Model
	2308-2DCG8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-2DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308-1DCG Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1DCG	3D model available Symbol and footprint available 3	1 Download Model
	2308-4DCGI Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-4DCGI	3D model available Symbol and footprint available 3	1 Download Model
	2308-2HDCGI8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-2HDCGI8	3D model available Symbol and footprint available 3	1 Download Model

	2308-5HPGGI Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-5HPGGI	3D model available Symbol and footprint available 3	1 Download Model
	2308-1DCG8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308-1DCGI8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1DCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308-1HDCG Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1HDCG	3D model available Symbol and footprint available 3	1 Download Model
	2308-3DCG8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-3DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308-4DCG Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-4DCG	3D model available Symbol and footprint available 3	1 Download Model
	2308-1HDCG8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1HDCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308-1HPGG8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1HPGG8	3D model available Symbol and footprint available 3	1 Download Model
	2308-5HPGGI8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-5HPGGI8	3D model available Symbol and footprint available 3	1 Download Model
	2308-4DCG8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-4DCG8	3D model not available Symbol and footprint available 2	1 Download Model
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