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Image Part Number D.S Description Package Category Prices / Stock Model Action
Image Part Number D.S Description Package Category Prices / Stock Model Action
Part Image Part Image 1 Inrush Current Limiters S236/2.2/M NTC Thermistor Other B57236S0229M000V9 1 Download Model
Part Image Part Image 1 Inrush Current Limiters 50 Ohms 1.9amps 3165k Other B57236S0500M000V9 1 Download Model
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TMUX7236RUMR Texas Instruments
1 Analog Switch ICs 44V, low-RON, 2:1 (SPDT) two-channel precision switch with latch-up immunity and 1.8V logic 16-WQFN -40 to 125 Quad Flat No-Lead TMUX7236RUMR 1 Download Model
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172361-10 Amphenol
1 RF Connectors / Coaxial Connectors 4H FLNG N TYPE STR JACK FLAT TAB 50 Ohm Other 172361-10 1 Download Model
Part Image Part Image 1 Inrush Current Limiters CORRECT MFG PN 871-B57236S0229M000 Other B57236S229MV9 1 Download Model
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BH7236AF-E2 ROHM Semiconductor
1 BH7236AF-E2, Video Encoder NTSC, PAL 5 V, 24-Pin SOP Small Outline Packages BH7236AF-E2 1 Download Model
Part Image Part Image 1 Inrush Current Limiters CORRECT MFG PN 871-B57236S0800M000 Other B57236S800MV9 1 Download Model
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CNY17-2-360E Avago Technologies
1 Optoisolator Transistor with Base Output 5000Vrms 1 Channel 6-SMD Small Outline Packages CNY17-2-360E 1 Download Model
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723623L12PFG Renesas Electronics
1 The 723623 is a 256 x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. Quad Flat Packages 723623L12PFG 1 Download Model
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723616L15PF8 Renesas Electronics
1 The 723616 is a 64 x 36 x 2 Triple Bus SyncFIFO memory which supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 x 36 dual-port SRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface. Quad Flat Packages 723616L15PF8 1 Download Model
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723632L15PFG Renesas Electronics
1 The 723632 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 512 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723632L15PFG 1 Download Model
Part Image Part Image 1 NTC Inrush Current Limiters, Resistance (at 25℃)=4.7Ω, Maximum Current=4.6A Other B57236S0479M000 1 Download Model
Part Image Part Image 1 NTC Inrush Current Limiters, Resistance (at 25℃)=120Ω, Maximum Current=1.5A Other B57236S0121M051 1 Download Model
Part Image Part Image 1 Connector, Wave soldering termination, Rated current: ?7.5 A, Female, Size: D-Sub 2, Thermoplastic resin (PCT), Plated steel, C-filter, 1000 pF Other 09642127236 1 Download Model
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R1QHA7236ABB-25IB1 Renesas Electronics
1 The R1Q#A7236 is a 2, 097, 152-word by 36-bit and the R1Q#A7218 is a 4, 194, 304-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed, low BGA R1QHA7236ABB-25IB1 1 Download Model
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723634L12PF Renesas Electronics
1 The 723634 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 512 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723634L12PF 1 Download Model
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723642L15PF Renesas Electronics
1 The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723642L15PF 1 Download Model
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723673L15PF Renesas Electronics
1 The 723673 is a 8K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. This device can operate in the IDT Standard mode Quad Flat Packages 723673L15PF 1 Download Model
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723656L15PF8 Renesas Electronics
1 The 723656 is a 2K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode. Quad Flat Packages 723656L15PF8 1 Download Model
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723634L15PF8 Renesas Electronics
1 The 723634 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 512 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723634L15PF8 1 Download Model
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723646L12PF Renesas Electronics
1 The 723646 is a 1K x 36 x 2 Triple Bus sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. FIFO data can be read out and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. The clocks for each port are independent of one another and can be asynchronous or coincident. Communication between each port may bypass the FIFOs via two mailbox registers. These devices can operate in the IDT Standard mode or First Wo Quad Flat Packages 723646L12PF 1 Download Model
Part Image Part Image 1 NTC Inrush Current Limiters, Resistance (at 25℃)=80Ω, Maximum Current=1.6A Other B57236S0800M000 1 Download Model
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SL617236GECO Fischer Elektronik GmbH & Co. KG
1 male header Other SL617236GECO 1 Download Model
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723663L12PF Renesas Electronics
1 The 723663 is a 4K x 36 unidirectional Sync FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8ns. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. This device can operate in the IDT Standard mode Quad Flat Packages 723663L12PF 1 Download Model
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723632L15PF Renesas Electronics
1 The 723632 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 512 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Quad Flat Packages 723632L15PF 1 Download Model
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