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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	7285L15PAGI8 Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L15PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	7285L20PA Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L20PA	3D model available Symbol and footprint available 3	1 Download Model
	7285L15PAI Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L15PAI	3D model available Symbol and footprint available 3	1 Download Model
	7285L12PAG Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L12PAG	3D model available Symbol and footprint available 3	1 Download Model

	7285L15PAI8 Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L15PAI8	3D model available Symbol and footprint available 3	1 Download Model
	7285L15PA8 Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L15PA8	3D model available Symbol and footprint available 3	1 Download Model
	7285L12PAG8 Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L12PAG8	3D model available Symbol and footprint available 3	1 Download Model
	7285L15PA Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L15PA	3D model available Symbol and footprint available 3	1 Download Model
	7285L12PA Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L12PA	3D model available Symbol and footprint available 3	1 Download Model
	7285L20PA8 Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L20PA8	3D model available Symbol and footprint available 3	1 Download Model
	7285L15PAGI Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L15PAGI	3D model available Symbol and footprint available 3	1 Download Model
	7285L12PA8 Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L12PA8	3D model available Symbol and footprint available 3	1 Download Model
	72T7285L4-4BBG Renesas Electronics	1	The 72T7285 is a 16K x 72 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x72/x36/x18 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode.	BGA	72T7285L4-4BBG	3D model available Symbol and footprint available 3	1 Download Model
	7285L15PAGI8 Integrated Device Technology Inc	1	FIFO, 8KX9, 15ns, Asynchronous, CMOS, PDSO56		7285L15PAGI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L15PAGI Integrated Device Technology Inc	1	FIFO, 8KX9, 15ns, Asynchronous, CMOS, PDSO56		7285L15PAGI	3D model not available Symbol and footprint not available 0	0 Build or Request

	7285L20PAI Integrated Device Technology Inc	1	FIFO, 8KX9, 20ns, Asynchronous, CMOS, PDSO56		7285L20PAI	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L15PAI Integrated Device Technology Inc	1	FIFO, 8KX9, 15ns, Asynchronous, CMOS, PDSO56		7285L15PAI	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L15PAG8 Integrated Device Technology Inc	1	FIFO, 8KX9, 15ns, Asynchronous, CMOS, PDSO56		7285L15PAG8	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L20PAG8 Integrated Device Technology Inc	1	FIFO, 8KX9, 20ns, Asynchronous, CMOS, PDSO56		7285L20PAG8	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L12PAG8 Integrated Device Technology Inc	1	FIFO, 8KX9, 12ns, Asynchronous, CMOS, PDSO56		7285L12PAG8	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L15PAG8I Integrated Device Technology Inc	1	FIFO		7285L15PAG8I	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L12PA8 Integrated Device Technology Inc	1	FIFO, 8KX9, 12ns, Asynchronous, CMOS, PDSO56		7285L12PA8	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L12PAGI Renesas Electronics Corporation	1	FIFO, 8KX9, 15ns, Asynchronous, CMOS, PDSO56		7285L12PAGI	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L20PAG Integrated Device Technology Inc	1	FIFO, 8KX9, 20ns, Asynchronous, CMOS, PDSO56		7285L20PAG	3D model not available Symbol and footprint not available 0	0 Build or Request
	7285L20PA8 Integrated Device Technology Inc	1	FIFO, 8KX9, 20ns, Asynchronous, CMOS, PDSO56		7285L20PA8	3D model not available Symbol and footprint not available 0	0 Build or Request
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