82V30 Footprint, Symbol and 3D Model search results

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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	82V3010PVG Renesas Electronics	1	The 82V3010 is a T1/E1/OC3 telecom clock generator with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3010 provides 9 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3010 is co	Small Outline Packages	82V3010PVG	3D model available Symbol and footprint available 3	1 Download Model
	82V3002APVG8 Renesas Electronics	1	The 82V3002A is a WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The 82V3002A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o, F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate transmission links. The 82V3002A is compliant with AT&T TR62411, Telcordia GR- 124	Small Outline Packages	82V3002APVG8	3D model available Symbol and footprint available 3	1 Download Model
	82V3002APVG Renesas Electronics	1	The 82V3002A is a WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The 82V3002A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o, F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate transmission links. The 82V3002A is compliant with AT&T TR62411, Telcordia GR- 124	Small Outline Packages	82V3002APVG	3D model available Symbol and footprint available 3	1 Download Model
	82V3001APVG Renesas Electronics	1	The 82V3001A is a WAN PLL with single reference input. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The 82V3001A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o, F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate transmission links. The 82V3001A is compliant with AT&T TR62411, Telcordia GR- 12	Small Outline Packages	82V3001APVG	3D model available Symbol and footprint available 3	1 Download Model

	82V3012PVG8 Renesas Electronics	1	The 82V3012 is a T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3012 provides 9 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3012 is compliant with AT&	Small Outline Packages	82V3012PVG8	3D model available Symbol and footprint available 3	1 Download Model
	82V3012PVG Renesas Electronics	1	The 82V3012 is a T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3012 provides 9 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3012 is compliant with AT&	Small Outline Packages	82V3012PVG	3D model available Symbol and footprint available 3	1 Download Model
	82V3010PVG8 Renesas Electronics	1	The 82V3010 is a T1/E1/OC3 telecom clock generator with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3010 provides 9 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3010 is co	Small Outline Packages	82V3010PVG8	3D model available Symbol and footprint available 3	1 Download Model
	82V3001APVG8 Renesas Electronics	1	The 82V3001A is a WAN PLL with single reference input. It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The 82V3001A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o, F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate transmission links. The 82V3001A is compliant with AT&T TR62411, Telcordia GR- 12	Small Outline Packages	82V3001APVG8	3D model available Symbol and footprint available 3	1 Download Model
	82V3011PVG Renesas Electronics	1	The 82V3011 is a T1/E1/OC3 WAN PLL with single reference input. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3011 provides 9 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3011 is compliant with AT	Small Outline Packages	82V3011PVG	3D model available Symbol and footprint available 3	1 Download Model
	82V3011PVG8 Renesas Electronics	1	The 82V3011 is a T1/E1/OC3 WAN PLL with single reference input. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS and 19.44 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3011 provides 9 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3011 is compliant with AT	Small Outline Packages	82V3011PVG8	3D model available Symbol and footprint available 3	1 Download Model
	82V3002APVG Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3002APVG	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3002APVG8 Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3002APVG8	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3010PV Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3010PV	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3002APV Renesas Electronics Corporation	1	PLL/Frequency Synthesis Circuit		82V3002APV	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3012PV8 Renesas Electronics Corporation	1	Telecom Circuit, 1-Func, PDSO56		82V3012PV8	3D model not available Symbol and footprint not available 0	0 Build or Request

	82V3012PVG Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3012PVG	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3002PV Integrated Device Technology Inc	1	ATM/SONET/SDH IC		82V3002PV	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3012PV Renesas Electronics Corporation	1	Telecom Circuit, 1-Func, PDSO56		82V3012PV	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3001APVG Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3001APVG	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V30113VG Renesas Electronics Corporation	1	Telecom Circuit		82V30113VG	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3011PVG Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3011PVG	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3001APV Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3001APV	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3002PV Renesas Electronics Corporation	1	PLL/Frequency Synthesis Circuit		82V3002PV	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3001APV8 Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3001APV8	3D model not available Symbol and footprint not available 0	0 Build or Request
	82V3011PVG8 Integrated Device Technology Inc	1	Telecom Circuit, 1-Func, PDSO56		82V3011PVG8	3D model not available Symbol and footprint not available 0	0 Build or Request
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