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W631GU6NB11I
Winbond
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1 | The W631GU6NB is a 1G bits DDR3L SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J | BGA | W631GU6NB11I |
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W631GU6NB15I
Winbond
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1 | The W631GU6NB is a 1G bits DDR3L SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J | BGA | W631GU6NB15I |
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W631GG6NB11J
Winbond
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1 | The W631GG6NB is a 1G bits DDR3 SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J | BGA | W631GG6NB11J |
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W631GG6NB-11
Winbond
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1 | The W631GG6NB is a 1G bits DDR3 SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J | BGA | W631GG6NB-11 |
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W631GU6NB12I
Winbond
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1 | The W631GU6NB is a 1G bits DDR3L SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J | BGA | W631GU6NB12I |
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W631GG6NB11I
Winbond
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1 | The W631GG6NB is a 1G bits DDR3 SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J | BGA | W631GG6NB11I |
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W631GU8NB-15
Winbond
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1 | The W631GU8NB is a 1G bits DDR3L SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J | BGA | W631GU8NB-15 |
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W631GU6MB12S
Winbond
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1 | 1Gb DDR3 SDRAM 1600MHz VFBGA96 | BGA | W631GU6MB12S |
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W631GG6MB15W
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w | BGA | W631GG6MB15W |
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W631GU8RB-09
Winbond
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1 | SDRAM - DDR3L Memory IC 1Gbit Parallel 800 MHz 20 ns 78-VFBGA (8x10.5) | BGA | W631GU8RB-09 |
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W631GG6MB12S
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w | BGA | W631GG6MB12S |
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W631GG8NB11S
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit | BGA | W631GG8NB11S |
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W631GU6RB11S
Winbond
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1 | 1Gb DDR3 SDRAM 1866MHz VFBGA96 | BGA | W631GU6RB11S |
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W631GU8RB-11
Winbond
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1 | 1Gb DDR3 SDRAM 1866MHz VFBGA78 | BGA | W631GU8RB-11 |
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W631GU6NB15S
Winbond
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1 | 1Gb DDR3 SDRAM 1333MHz VFBGA96 | BGA | W631GU6NB15S |
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W631GG6NB11S
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V⚫ Double Data Rate architecture: two data transfers per clock cycle⚫ Eight internal banks for concurrent operation⚫ 8 bit prefetch architecture⚫ CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14⚫ Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)⚫ Programmable read burst ordering: interleaved or nibble sequential⚫ Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit | BGA | W631GG6NB11S |
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W631GG6NB09A
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w | BGA | W631GG6NB09A |
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W631GU6RB12I
Winbond
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1 | 1Gb DDR3 SDRAM 1600MHz VFBGA96 | BGA | W631GU6RB12I |
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W631GU6MB11S
Winbond
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1 | Power Supply: 1.35V (typ.), VDD, VDDQ = 1.283V to 1.45V Backward compatible to VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, d | BGA | W631GU6MB11S |
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W631GG6NB12K
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V⚫ Double Data Rate architecture: two data transfers per clock cycle⚫ Eight internal banks for concurrent operation⚫ 8 bit prefetch architecture⚫ CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14⚫ Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)⚫ Programmable read burst ordering: interleaved or nibble sequential⚫ Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit | BGA | W631GG6NB12K |
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W631GG8NB11A
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit | BGA | W631GG8NB11A |
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W631GU8MB09K
Winbond
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1 | SDRAM - DDR3L Memory IC 1Gbit Parallel 800 MHz 20 ns 78-VFBGA (10.5x8) | BGA | W631GU8MB09K |
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W631GG8MB11W
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w | BGA | W631GG8MB11W |
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W631GU6MB11W
Winbond
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1 | Power Supply: 1.35V (typ.), VDD, VDDQ = 1.283V to 1.45V Backward compatible to VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, d | BGA | W631GU6MB11W |
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W631GU6NB09S
Winbond
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1 | 1Gb DDR3 SDRAM 2133MHz VFBGA96 | BGA | W631GU6NB09S |
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