Description:The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.
IT CAN ALSO BE CONFIGURED AS 32K X 9; RETRANSMIT; ASYNCHRONOUS MODE IS ALSO POSSIBLE
Alternate Memory Width:
9
Clock Frequency-Max (fCLK):
100 MHz
Cycle Time:
10 ns
JESD-30 Code:
S-PQFP-G80
JESD-609 Code:
e3
Length:
14 mm
Memory Density:
294912 bit
Memory IC Type:
OTHER FIFO
Memory Width:
18
Moisture Sensitivity Level:
3
Number of Functions:
1
Number of Terminals:
80
Number of Words:
16384 words
Number of Words Code:
16000
Operating Mode:
SYNCHRONOUS
Operating Temperature-Max:
70 °C
Organization:
16KX18
Output Enable:
YES
Package Body Material:
PLASTIC/EPOXY
Package Code:
LQFP
Package Equivalence Code:
QFP80,.64SQ
Package Shape:
SQUARE
Package Style:
FLATPACK, LOW PROFILE
Parallel/Serial:
PARALLEL
Peak Reflow Temperature (Cel):
260
Qualification Status:
Not Qualified
Seated Height-Max:
1.6 mm
Standby Current-Max:
0.015 A
Supply Current-Max:
0.035 mA
Supply Voltage-Max (Vsup):
3.45 V
Supply Voltage-Min (Vsup):
3.15 V
Supply Voltage-Nom (Vsup):
3.3 V
Surface Mount:
YES
Technology:
CMOS
Temperature Grade:
COMMERCIAL
Terminal Finish:
MATTE TIN
Terminal Form:
GULL WING
Terminal Pitch:
0.65 mm
Terminal Position:
QUAD
Time@Peak Reflow Temperature-Max (s):
30
Width:
14 mm
72V273L10PFG Frequently Asked Questions (FAQs)
Renesas provides a recommended PCB layout guide in their application note (APN) documents, which includes guidelines for thermal vias, copper pours, and component placement to ensure optimal thermal performance.
To ensure reliable operation in high-temperature environments, it's essential to follow the recommended operating conditions, use a suitable heat sink, and implement thermal monitoring and protection mechanisms, such as thermal shutdown or warning signals.
The datasheet recommends using multiple decoupling capacitors with a total capacitance of at least 100nF, placed as close as possible to the power pins, to ensure stable operation and reduce noise.
The 72V273L10PFG requires a specific power sequencing and startup procedure to ensure proper operation. This typically involves powering up the voltage regulator in a specific order, and using external components such as resistors and capacitors to control the startup sequence.
When using the 72V273L10PFG in a high-current application, it's essential to consider the device's current rating, thermal performance, and power dissipation. Additionally, the PCB design should be optimized for high-current flow, and the device may require additional heat sinking or cooling mechanisms.
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72V273L10PFG Overview
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