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XC6SLX25-2FGG484C - AMD

Description: FPGA Spartan-6 24051 logic cells FBGA484 XC6SLX25-2FGG484C, FPGA Spartan-6 24051 Cells, 936kbit, 15000 Blocks, 484-Pin FPBGA

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XC6SLX25-2FGG484C - AMD PCB footprint - BGA - BGA - FGG484
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XC6SLX25-2FGG484C - AMD  - 3D model - BGA - FGG484
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XC6SLX25-2FGG484C Details

  • Manufacturer Part Number:

    XC6SLX25-2FGG484C

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-484

  • Country Of Origin:

    Taiwan

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    12 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    4

  • Clock Frequency-Max:

    667 MHz

  • Combinatorial Delay of a CLB-Max:

    0.26 ns

  • JESD-30 Code:

    S-PBGA-B484

  • JESD-609 Code:

    e1

  • Length:

    23 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    1879

  • Number of Inputs:

    266

  • Number of Logic Cells:

    24051

  • Number of Outputs:

    266

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    85 °C

  • Organization:

    1879 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA484,22X22,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 40 nm

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    23 mm

XC6SLX25-2FGG484C Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the XC6SLX25 is 350 MHz.
  • You can implement DDR3 memory interface using the MIG (Memory Interface Generator) tool provided by Xilinx, which generates a customized IP core for the DDR3 interface.
  • The power consumption of XC6SLX25 varies depending on the operating frequency, voltage, and usage. However, the typical power consumption is around 1.5W to 2.5W.
  • Yes, XC6SLX25 is suitable for high-reliability applications, such as aerospace, defense, and medical devices, due to its radiation-hardened design and error correction capabilities.
  • You can optimize the design for area and speed by using Xilinx's Vivado Design Suite, which provides various optimization techniques, such as pipelining, retiming, and resource sharing.

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XC6SLX25-2FGG484C Overview

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Image Part Number Model
Part Image XC6SLX25-2FGG484I AMD Xilinx

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

Part Image XC6SLX25-2FGG484C AMD Xilinx

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

Part Image XC6SLX25-2FG484I AMD

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

Part Image XC6SLX25-2FG484C AMD

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

Part Image XC6SLX25-2FG484I AMD Xilinx

Field Programmable Gate Array, 1879 CLBs, 667MHz, 24051-Cell, CMOS, PBGA484

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