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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	SY75707TWL-TR Microchip	1	Clock Buffer 1 to 2 SE Fanout Buffer	Small Outline No-lead	SY75707TWL-TR	3D model available Symbol and footprint available 3	1 Download Model
	671M-01LF Renesas Electronics	1	Zero Delay, Low Skew Buffer and Multiplier	Small Outline Packages	671M-01LF	3D model available Symbol and footprint available 3	1 Download Model
	9DBU0741AKILF Renesas Electronics	1	The 9DBU0741 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 ohm transmission lines. The device has 7 output enables for clock management, and 3 selectable SMBus addresses.	Quad Flat No-Lead	9DBU0741AKILF	3D model available Symbol and footprint available 3	1 Download Model
	PI6CB33601ZLAIEX Diodes Incorporated This part was updated within the past 30 days. Set alerts for model updates on the part download page.	1	Clock Fanout Buffer (Distribution) IC 1:6 133.33 MHz 40-WFQFN Exposed Pad	Quad Flat No-Lead	PI6CB33601ZLAIEX	3D model available Symbol and footprint available 3	1 Download Model

	8T33FS314PYGI Renesas Electronics	1	The IDT8T33FS314I is a low skew 1-to-4 Differential Fanout Buffer, designed with clock distribution in mind, accepting two clock sources into an input MUX. The MUX is controlled by a CLK_SEL pin. This makes the IDT8T33FS314I very versatile, in that, it can operate as both a differential clock buffer as well as a signal-level translator and fanout buffer. The device is designed on a SiGe process and can operate at frequencies in excess of 2.7GHz. This ensures negligible jitter introduction to the timing budg	Small Outline Packages	8T33FS314PYGI	3D model available Symbol and footprint available 3	1 Download Model
	8T49N488A-999ASGI Renesas Electronics	1	The IDT8T49N488I is a quad PLL with FemtoClock® NG technology, integrating low phase noise Frequency Translator / Synthesizer, Jitter attenuator, and alarm and monitoring functions suitable for networking and communications applications. The device has four fully independent PLLs, each PLL is able to generate any output frequency in the 0.98MHz - 312.5MHz range and most output frequencies in the 312.5MHz - 1,300MHz range. A wide range of input reference clocks and operation reference clock may be used as th	BGA	8T49N488A-999ASGI	3D model available Symbol and footprint available 3	1 Download Model
	853S012AKILFT Renesas Electronics	1	The 853S012I is an 12:1 Differential-to-3.3V or 2.5V LVPECL Clock/Data Multiplexer which can operate up to 3.2GHz. The 853S012I has twelve differential selectable clock inputs. The CLK, nCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors.	Quad Flat No-Lead	853S012AKILFT	3D model available Symbol and footprint available 3	1 Download Model
	551SCMGI8 Renesas Electronics	1	The 551S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 551S has best in class Additive Phase Jitter of sub 50 fsec.	Small Outline No-lead	551SCMGI8	3D model available Symbol and footprint available 3	1 Download Model
	8525BGLFT Renesas Electronics	1	The 8525 is a low skew, high performance 1-to-4 LVCMOS-to-LVHSTL fanout buffer. The 8525 has two selectable clock inputs thataccept LVCMOS or LVTTL input levels and translate them to LVHSTL levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8525 ideal for those applications demanding well defined performance and repeatability.	Small Outline Packages	8525BGLFT	3D model available Symbol and footprint available 3	1 Download Model
	551SCMGI Renesas Electronics	1	The 551S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 551S has best in class Additive Phase Jitter of sub 50 fsec.	Small Outline No-lead	551SCMGI	3D model available Symbol and footprint available 3	1 Download Model
	9DB433AGLFT Renesas Electronics	1	The 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.	Small Outline Packages	9DB433AGLFT	3D model available Symbol and footprint available 3	1 Download Model
	98ULPA877AKLF Renesas Electronics	1	1.8V Low power 1 to 10 differential clock distribution. Operating frequency: 125MHz to 410MHz	Quad Flat No-Lead	98ULPA877AKLF	3D model available Symbol and footprint available 3	1 Download Model
	5V2305NRGI8 Renesas Electronics	1	The IDT5V2305 is a high performance, low skew clock buffer that operates up to 200MHz. One bank of five outputs provides low skew copies of CLK. Through the use of control pin G, the outputs of bank Y(0:4) can be placed in a low state regardless of CLK input. The device operates in 2.5V and 3.3V environments. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. The IDT5V2305 is characterized for operation from -40°C to +85°C.	Other	5V2305NRGI8	3D model available Symbol and footprint available 3	1 Download Model
	MPC9456AC Renesas Electronics	1	The MPC9456 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer designed for low-voltage mid-range to high-performance telecom, networking and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage applications. The MPC9456 offers 10 low-skew outputs and a differential LVPECL clock input. The outputs are configurable and support 1:1 and 1:2 output to input frequency ratios. The MPC9456 is specified for the extended temperature range of –40 to 85°C.	Quad Flat Packages	MPC9456AC	3D model available Symbol and footprint available 3	1 Download Model
	527R-01ILFT Renesas Electronics	1	The 527-01 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MH	Small Outline Packages	527R-01ILFT	3D model available Symbol and footprint available 3	1 Download Model

	854S057BGILFT Renesas Electronics	1	The 854S057BI is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz. The PCLK, nPCLK pairs can accept most standard differential input levels. Internal termination is provided on each differential input pair. The 854S057BI operates using a 2.5V supply voltage. The fully differential architecture and low propagation delay make it ideal for use in high speed multiplexing applications. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the inte	Small Outline Packages	854S057BGILFT	3D model available Symbol and footprint available 3	1 Download Model
	23S09E-1HPGG Renesas Electronics	1	3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible	Small Outline Packages	23S09E-1HPGG	3D model available Symbol and footprint available 3	1 Download Model
	9DBU0841AKILF Renesas Electronics	1	The 9DBU0841 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. It has integrated output terminations providing Zo=100 ohms for direct connection to 100 ohm transmission lines. The device has 8 output enables for clock management and 3 selectable SMBus addresses.	Quad Flat No-Lead	9DBU0841AKILF	3D model available Symbol and footprint available 3	1 Download Model
	PI49FCT3805DQE Diodes Incorporated	1	Clock Fanout Buffer (Distribution) IC 1:5 133 MHz 20-SSOP (0.154", 3.90mm Width)	Small Outline Packages	PI49FCT3805DQE	3D model available Symbol and footprint available 3	1 Download Model
	2309-1HPGG8 Renesas Electronics	1	The 2309 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on ICS' proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides nine low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The 2309 is available in two different versions. The 23	Small Outline Packages	2309-1HPGG8	3D model available Symbol and footprint available 3	1 Download Model
	9DBL411BGLFT Renesas Electronics	1	The 9DBL411 is a four output lower power differential buffer. Each output has its own OE# pin. The device has a maximum operating frequency of 150MHz.	Small Outline Packages	9DBL411BGLFT	3D model available Symbol and footprint available 3	1 Download Model
	2305B-1DCG8 Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1DCG8	3D model available Symbol and footprint available 3	1 Download Model
	PI6C20400ALEX Diodes Incorporated	1	Clock Buffer 1:4 PCI Express Gen 2 Zero Delay Buffer	Small Outline Packages	PI6C20400ALEX	3D model available Symbol and footprint available 3	1 Download Model
	9DBL0641CKILF Renesas Electronics	1	The 9DBL0641 6-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0641 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures. For information regarding evaluation boards and material, please contact your local sales representative.	Quad Flat No-Lead	9DBL0641CKILF	3D model available Symbol and footprint available 3	1 Download Model
	9DB106BFLF Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BFLF	3D model available Symbol and footprint available 3	1 Download Model
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