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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	AL460A-7-PBF AverLogic	1	AverLogic AL460A-7-PBF, FIFO Memory, Single 128Mbit, 8M x 16, Uni-Directional 105MHz, 2.5 → 3.3 V, 128-Pin LQFP	Quad Flat Packages	AL460A-7-PBF	3D model available Symbol and footprint available 3	1 Download Model
	SN74ALVC7806-25DL Texas Instruments	1	FIFO 16-Bit Edg-Trig D-Ty F-F W/3-State Otpt	Small Outline Packages	SN74ALVC7806-25DL	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7811-20PN Texas Instruments	1	IC SYNC FIFO MEM 1024X18 80-LQFP	Quad Flat Packages	SN74ACT7811-20PN	3D model available Symbol and footprint available 3	1 Download Model
	IDT7206L15JG Renesas Electronics	1	IDT IDT7206L15JG, FIFO Memory, Dual 144kbit, 16K x 9 bit, Bi-Directional 15ns, 4.5 → 5.5 V, 32-Pin PLCC	Plastic Leaded Chip Carrier	IDT7206L15JG	3D model not available Symbol and footprint available 2	1 Download Model

	CD74HC40105M96E4 Texas Instruments	1	Registers 4bits x 16words FIFO	Small Outline Packages	CD74HC40105M96E4	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7805-25DLR Texas Instruments	1	FIFO 256 x 18 synchronous FIFO memory	Small Outline Packages	SN74ACT7805-25DLR	3D model available Symbol and footprint available 3	1 Download Model
	IDT72T36125L5BBI Renesas Electronics	1	IDT IDT72T36125L5BBI, FIFO Memory, Dual, 256K x 36 bit, Uni-Directional 10ns 200MHz, 2.375 → 2.625 V, 240-Pin BGA	BGA	IDT72T36125L5BBI	3D model available Symbol and footprint available 3	1 Download Model
	SN74ALS236N Texas Instruments	1	IC MEMORY 64X4 ASYNCH 16-DIP	Dual-In-Line Packages	SN74ALS236N	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L7-5BB8 Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model
	72255LA15PFGI8 Renesas Electronics	1	The 72255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72255LA15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V251L10PFG8 Renesas Electronics	1	The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V251L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V845L15PFGI8 Renesas Electronics	1	The 72V845 is a 4K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V245 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V845L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V3640L7-5BB Renesas Electronics	1	The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3640L7-5BB	3D model available Symbol and footprint available 3	1 Download Model
	72T1845L5BB Renesas Electronics	1	The 72T1845 is a 2K x 18 / 4K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1845L5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V253L7-5PFGI8 Renesas Electronics	1	The 72V253 8K x 9/4K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V253L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model

	72V253L6BCG Renesas Electronics	1	The 72V253 8K x 9/4K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V253L6BCG	3D model available Symbol and footprint available 3	1 Download Model
	72V293L6PFG Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V293L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3670L6BB Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3670L6BB	3D model available Symbol and footprint available 3	1 Download Model
	7283L15PAGI8 Renesas Electronics	1	The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7283L15PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V02L15JG Renesas Electronics	1	The 72V02 is a 1K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V02L15JG	3D model available Symbol and footprint available 3	1 Download Model
	7207L15JG8 Renesas Electronics	1	The 7207 is a 32K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7207L15JG8	3D model not available Symbol and footprint available 2	1 Download Model
	72T36125L5BBGI Renesas Electronics	1	The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36125L5BBGI	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L7-5PFGI8 Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72221L10PFG8 Renesas Electronics	1	The 72221SyncFIFO™ is a 1K x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72221L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V281L15TFGI8 Renesas Electronics	1	The 72V281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72281 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V281L15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
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