SRAMs Footprint, Symbol and 3D Model search results

Showing 25 of 562704 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71T75602S166PFG8 Renesas Electronics	1	The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75602 contains data I/O, address and control signal registers.	Quad Flat Packages	71T75602S166PFG8	3D model available Symbol and footprint available 3	1 Download Model
	7134LA20PDG Renesas Electronics	1	The 7134 is a high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same Dual-Port RAM location. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade prod	Dual-In-Line Packages	7134LA20PDG	3D model available Symbol and footprint available 3	1 Download Model
	5962-8861010ZA Renesas Electronics	1	The 5962-88610 (IDT 7133/43) is a high-speed 2K x 16 Dual-Port Static RAMs. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Military grade product in compliance with MIL-PRF-38535 QML.	Other	5962-8861010ZA	3D model available Symbol and footprint available 3	1 Download Model
	7008L15JG Renesas Electronics	1	The 7008 is a high-speed 64K x 8 Dual-Port Static RAM designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Plastic Leaded Chip Carrier	7008L15JG	3D model not available Symbol and footprint available 2	1 Download Model

	71V3556SA100BGGI8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA100BGGI8	3D model available Symbol and footprint available 3	1 Download Model
	70T651S12BCI8 Renesas Electronics	1	The 70T651 is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T651S12BCI8	3D model available Symbol and footprint available 3	1 Download Model
	71V416L10BE Renesas Electronics	1	The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	BGA	71V416L10BE	3D model available Symbol and footprint available 3	1 Download Model
	71124S20YGI8 Renesas Electronics	1	The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71124S20YGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V67703S80BQG Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V67703S80BQG	3D model available Symbol and footprint available 3	1 Download Model
	70V07L25PFG8 Renesas Electronics	1	The 70V07 is a high-speed 32K x 8 Dual-Port Static RAM designed to be used as a stand-alone 256K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit-or-more word systems which results in full speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	70V07L25PFG8	3D model available Symbol and footprint available 3	1 Download Model
	70V3589S133DRG8 Renesas Electronics	1	The 70V3589 is a high-speed 64K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3589 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	Quad Flat Packages	70V3589S133DRG8	3D model available Symbol and footprint available 3	1 Download Model
	70T653MS10BCG Renesas Electronics	1	The 70T653M is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone 18874K-bit Dual-Port RAM. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T653MS10BCG	3D model available Symbol and footprint available 3	1 Download Model
	70V06L20JGI8 Renesas Electronics	1	The 70V06 is a high-speed 16K x 8 Dual-Port Static RAM designed to be used as a stand-alone 128K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bit-or-more word systems which results in full speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Plastic Leaded Chip Carrier	70V06L20JGI8	3D model not available Symbol and footprint available 2	1 Download Model
	70V3569S5BCI8 Renesas Electronics	1	The 70V3569 is a high-speed 16K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3569 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	BGA	70V3569S5BCI8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA100BGI8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BGI8	3D model available Symbol and footprint available 3	1 Download Model

	70V639S10BF Renesas Electronics	1	The 70V639 is a high-speed 128K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po	BGA	70V639S10BF	3D model available Symbol and footprint available 3	1 Download Model
	71V25761S166PFG8 Renesas Electronics	1	The 71V25761 3.3V CMOS Synchronous SRAM is organized as 128K x 36 and contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V25761 can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V25761S166PFG8	3D model available Symbol and footprint available 3	1 Download Model
	70V9279L7PRFG Renesas Electronics	1	The 70V9279 is a high-speed 32K x 16 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	70V9279L7PRFG	3D model available Symbol and footprint available 3	1 Download Model
	70T653MS12BC8 Renesas Electronics	1	The 70T653M is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone 18874K-bit Dual-Port RAM. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T653MS12BC8	3D model available Symbol and footprint available 3	1 Download Model
	71V416L12BEI8 Renesas Electronics	1	The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	BGA	71V416L12BEI8	3D model available Symbol and footprint available 3	1 Download Model
	7027L20PFGI Renesas Electronics	1	The 7027 is a high-speed 32K x 16 Dual-Port Static RAM designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. An automatic power down feature permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Quad Flat Packages	7027L20PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V424L15YGI Renesas Electronics	1	The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71V424L15YGI	3D model available Symbol and footprint available 3	1 Download Model
	7026L35G Renesas Electronics	1	The 7026 is a high-speed 16K x 16 Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7026L35G	3D model available Symbol and footprint available 3	1 Download Model
	71V3556SA100BQGI8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	BGA	71V3556SA100BQGI8	3D model available Symbol and footprint available 3	1 Download Model
	71T75802S133BGI Renesas Electronics	1	The 71T75802 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75802 contains data I/O, address and control signal registers.	BGA	71T75802S133BGI	3D model available Symbol and footprint available 3	1 Download Model
8 9 10 11 12 13 14 15 16

Can't find what you're looking for? Request this part

SRAMs Model Download Search Results

Popular SRAMs