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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	5962-8700214ZA Renesas Electronics	0	The 5962-87002 (IDT 7132/42) is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with M	Ceramic Dual-In-Line Packages	5962-8700214ZA	3D model not available Symbol and footprint available 2	1 Download Model
	7164L55DB Renesas Electronics	1	The 7164 5V CMOS SRAM is organized as 8K x 8. The 7164 offers a reduced power standby mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	7164L55DB	3D model not available Symbol and footprint available 2	1 Download Model
	71V65603S133BGGI8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S133BGGI8	3D model available Symbol and footprint available 3	1 Download Model
	71T75602S150BGI8 Renesas Electronics	1	The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75602 contains data I/O, address and control signal registers.	BGA	71T75602S150BGI8	3D model available Symbol and footprint available 3	1 Download Model

	71V3557S80BG8 Renesas Electronics	1	The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3557 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).	BGA	71V3557S80BG8	3D model available Symbol and footprint available 3	1 Download Model
	R1RW0416DSB-0PR#S1 Renesas Electronics	1	The R1RW0416D is a 4-Mbit High-Speed static RAM organized 256-kword × 16-bit. It has realized High-Speed access time by employing CMOS process (6-transistor memory cell) and High-Speed circuit designing technology. It is most appropriate for the application which requires High-Speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. Especially, LVersion and S-Version are low power consumption and it is the best for the battery backup system. The package prepare	Small Outline Packages	R1RW0416DSB-0PR#S1	3D model available Symbol and footprint available 3	1 Download Model
	RMWV6416AGSD-5S2#AA0 Renesas Electronics	1	The RMWV6416A Series is a family of 64-Mbit static RAMs organized 4, 194, 304-word × 16-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMWV6416A Series has realized higher density, higher performance and low power consumption. The RMWV6416A Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 48pin TSOP (I), 52pin TSOP (II) or 48-ball fine pitch ball grid array.	Small Outline Packages	RMWV6416AGSD-5S2#AA0	3D model available Symbol and footprint available 3	1 Download Model
	7164L70TDB Renesas Electronics	1	The 7164 5V CMOS SRAM is organized as 8K x 8. The 7164 offers a reduced power standby mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	7164L70TDB	3D model not available Symbol and footprint available 2	1 Download Model
	70V657S10BF Renesas Electronics	1	The 70V657 is a high-speed 32K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	BGA	70V657S10BF	3D model available Symbol and footprint available 3	1 Download Model
	71V016SA10YG Renesas Electronics	1	The 71V016 3.3V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71V016SA10YG	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S100BQG Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S100BQG	3D model available Symbol and footprint available 3	1 Download Model
	71V632S7PFGI8 Renesas Electronics	1	The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V632S7PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	70T3519S133BFI Renesas Electronics	1	The 70T3519 is a high-speed 256K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3519 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3519S133BFI	3D model available Symbol and footprint available 3	1 Download Model
	71V124SA12TYGI8 Renesas Electronics	1	The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71V124SA12TYGI8	3D model available Symbol and footprint available 3	1 Download Model
	7006L17G Renesas Electronics	1	The 7006 is a high-speed 16K x 8 Dual-Port Static RAM designed to be used as a stand-alone 128K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7006L17G	3D model available Symbol and footprint available 3	1 Download Model

	7005S35G Renesas Electronics	1	The 7005 is a high-speed 8K x 8 Dual-Port Static RAM designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7005S35G	3D model available Symbol and footprint available 3	1 Download Model
	RMLV0816BGSB-4S2#AA0 Renesas Electronics	1	The RMLV0816BGSB is a family of 8-Mbit static RAMs organized 524, 288-word × 16-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV0816BGSB has realized higher density, higher performance and low power consumption. The RMLV0816BGSB offers low power standby power dissipation;therefore, it is suitable for battery backup systems. It is offered in 44pin TSOP (II).	Small Outline Packages	RMLV0816BGSB-4S2#AA0	3D model available Symbol and footprint available 3	1 Download Model
	70T3519S200BCG Renesas Electronics	1	The 70T3519 is a high-speed 256K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3519 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3519S200BCG	3D model available Symbol and footprint available 3	1 Download Model
	71V35761SA166BQG8 Renesas Electronics	1	The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM.	BGA	71V35761SA166BQG8	3D model available Symbol and footprint available 3	1 Download Model
	71V35761SA166BQG Renesas Electronics	1	The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM.	BGA	71V35761SA166BQG	3D model available Symbol and footprint available 3	1 Download Model
	70V3579S5BC8 Renesas Electronics	1	The 70V3579 is a high-speed 32K × 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3579 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	BGA	70V3579S5BC8	3D model available Symbol and footprint available 3	1 Download Model
	71256L45TDB Renesas Electronics	1	The 71256 5V CMOS SRAM is organized as 32K x 8. The circuit also offers a reduced power standby mode for significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability allowing operation off a 2V battery. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	71256L45TDB	3D model not available Symbol and footprint available 2	1 Download Model
	709099L9PFGI Renesas Electronics	1	The 709099 is a high-speed 128K x 8 bit synchronous Dual- Port RAM. Registers on control, data, and address inputs provide minimal setup and hold times allowing systems to be designed with very short cycle times. With an input data register, it has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	709099L9PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S150PFG8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S150PFG8	3D model available Symbol and footprint available 3	1 Download Model
	RMLV1616AGSD-5S2#AC0 Renesas Electronics	1	The RMLV1616A Series is a family of 16-Mbit static RAMs organized 1, 048, 576-word × 16-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV1616A Series has realized higher density, higher performance and low power consumption. The RMLV1616A Series offers low power standby power dissipation;therefore, it is suitable for battery backup systems. It is offered in 48pin TSOP (I), 52pin TSOP (II) or 48-ball fine pitch ball grid array.	Small Outline Packages	RMLV1616AGSD-5S2#AC0	3D model available Symbol and footprint available 3	1 Download Model
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