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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	CAT24C02VP2I-GT3A Rochester Electronics	1	A	Small Outline No-lead	CAT24C02VP2I-GT3A	3D model available Symbol and footprint available 3	1 Download Model
	24CSM01T-E/SM Microchip	1	EEPROM 1024K I2C EEPROM, Ext Temp, 8-SOIJ	Small Outline Packages	24CSM01T-E/SM	3D model available Symbol and footprint available 3	1 Download Model
	24LC32A-I/P Microchip	1	IC,EEPROM,32KBIT,SERIAL,400KHZ	Dual-In-Line Packages	24LC32A-I/P	3D model available Symbol and footprint available 3	1 Download Model
	24LC16BHT-I/OT Microchip	1	Microchip 24LC16BHT-I/OT EEPROM Memory, 16kb, 900ns, 2.5 → 5.5 V SOT-23 5-Pin	SOT23 (5-Pin)	24LC16BHT-I/OT	3D model available Symbol and footprint available 3	1 Download Model

	AT24C164-10SC-1.8 QUANTUM ATMEL	1	Low Voltage and Standard Voltage Operation	Small Outline Packages	AT24C164-10SC-1.8	3D model available Symbol and footprint available 3	1 Download Model
	AT28HC64B-12SU-T Microchip	1	EEPROM 120NS, SOIC, IND TEMP, GREEN	Small Outline Packages	AT28HC64B-12SU-T	3D model available Symbol and footprint available 3	1 Download Model
	24FC256-I/ST Microchip	1	256K 32Kx8 2.5V Ser. EEPROM,24FC256-I/ST	Small Outline Packages	24FC256-I/ST	3D model available Symbol and footprint available 3	1 Download Model
	AT25HP512-10PI-2.7 Microchip	1	EEPROM Memory IC 512Kbit SPI 10 MHz 8-PDIPEEPROM Memory IC 512Kbit SPI 10 MHz 8-PDIP	Dual-In-Line Packages	AT25HP512-10PI-2.7	3D model available Symbol and footprint available 3	1 Download Model
	MT48LC4M16A2P Micron	1	tsop-54-11	Small Outline Packages	MT48LC4M16A2P	3D model available Symbol and footprint available 3	1 Download Model
	EDB8132B4PB-8D-F-D Micron	1	DRAM Chip Mobile LPDDR2 SDRAM 8Gbit 256Mx32 1.8V/1.2V 168-Pin FBGA Tray	BGA	EDB8132B4PB-8D-F-D	3D model available Symbol and footprint available 3	1 Download Model
	HY57V28820AT-H Hynix	1	4Banks x 4M x 8bits Synchronous DRAM	Small Outline Packages	HY57V28820AT-H	3D model available Symbol and footprint available 3	1 Download Model
	M27C256B-12F6 STMicroelectronics	1	UV EPROM and OTP EPROM	Ceramic Dual-In-Line Packages	M27C256B-12F6	3D model not available Symbol and footprint available 2	1 Download Model
	M27C2001-10F1 STMicroelectronics	1	EPROM	Ceramic Dual-In-Line Packages	M27C2001-10F1	3D model not available Symbol and footprint available 2	1 Download Model
	72V3660L7-5BB Renesas Electronics	1	The 72V3660 4K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3660L7-5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L7-5PFGI Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3690L7-5PFGI	3D model available Symbol and footprint available 3	1 Download Model

	723651L20PFGI Renesas Electronics	1	The 723651 is a 2K x 36 Sync FIFO memory that supports clock frequencies up to 67 MHz and has read access times as fast as 12ns. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. Communication between each port may take place with two 36-bit mailbox registers. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous port clock by enable signals.	Quad Flat Packages	723651L20PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V05L15JG Renesas Electronics	1	The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V05L15JG	3D model available Symbol and footprint available 3	1 Download Model
	72V3670L10PFG Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3670L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3660L7-5BB8 Renesas Electronics	1	The 72V3660 4K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3660L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V201L10PFG8 Renesas Electronics	1	The 72V201 is a 256 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72201 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V201L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V3672L10PFG Renesas Electronics	1	The 72V3672 Bidirectional SyncFIFO (clocked) memory is a 3.3V version of the 723672. Two independent 8K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	72V3672L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	7205L20TDB Renesas Electronics	1	The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7205L20TDB	3D model not available Symbol and footprint available 2	1 Download Model
	72V831L10PFG Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	7201LA50DB Renesas Electronics	1	The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7201LA50DB	3D model not available Symbol and footprint available 2	1 Download Model
	72261LA15TFGI8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
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