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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	SDB207-TP-B002 MCC	1	2 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts	Small Outline Packages	SDB207-TP-B002	3D model available Symbol and footprint available 3	1 Download Model
	SE2435L-R Skyworks	1	RF Front End 860-930MHz NF 2 dB Rx Gain 16 dB	Quad Flat No-Lead	SE2435L-R	3D model available Symbol and footprint available 3	1 Download Model
	MPKPCM-97H45P-40DB-4808 Multicomp Pro	1	Microphone, Omnidirectional, 2.2 kohm, -40 dB Sensitivity, 60 dB SNR, 2 Pins, 4.5 to 10 VDC	Other	MPKPCM-97H45P-40DB-4808	3D model available Symbol and footprint available 3	1 Download Model
	DB207L-BP MCC	1	2 Amp Single Phase Glass Passivated Bridge Rectifier 50 - 1000 Volts	Other	DB207L-BP	3D model available Symbol and footprint available 3	1 Download Model

	YAT-2A+ Mini-Circuits	1	2 dB SMT Fixed Attenuator, DC - 18000 MHz, 50Ω	Other	YAT-2A+	3D model available Symbol and footprint available 3	1 Download Model
	POM-3535P-3-R PUI Audio	1	Microphones MICROPHONE -35 DB 2 VDC .5 MA 2.2 KOHM	Other	POM-3535P-3-R	3D model available Symbol and footprint available 3	1 Download Model
	RCAT-02+ Mini-Circuits	1	2 dB SMT Fixed Attenuator, DC - 20000 MHz, 50Ω	Other	RCAT-02+	3D model not available Symbol and footprint available 2	1 Download Model
	9DB233AFLF Renesas Electronics	1	The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D	Small Outline Packages	9DB233AFLF	3D model available Symbol and footprint available 3	1 Download Model
	9DB233AFILF Renesas Electronics	1	The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D	Small Outline Packages	9DB233AFILF	3D model available Symbol and footprint available 3	1 Download Model
	9DB233AGLF Renesas Electronics	1	The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D	Small Outline Packages	9DB233AGLF	3D model available Symbol and footprint available 3	1 Download Model
	9DB233AGILF Renesas Electronics	1	The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D	Small Outline Packages	9DB233AGILF	3D model available Symbol and footprint available 3	1 Download Model
	9DB233AFLFT Renesas Electronics	1	The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D	Small Outline Packages	9DB233AFLFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB233AGILFT Renesas Electronics	1	The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D	Small Outline Packages	9DB233AGILFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB233AGLFT Renesas Electronics	1	The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D	Small Outline Packages	9DB233AGLFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB233AFILFT Renesas Electronics	1	The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9D	Small Outline Packages	9DB233AFILFT	3D model available Symbol and footprint available 3	1 Download Model

	ECS-45K30A ECS	1	Signal Conditioning 45.000 MHz Crystal Filter 3 dB BW +/-15 KHz 2 pole UM-1	Other	ECS-45K30A	3D model available Symbol and footprint available 3	1 Download Model
	BAT-2+ Mini-Circuits	1	Attenuators 2 dB MMIC SMT Fixed Attenuator, DC - 60 GHz, 50 Ohm	Other	BAT-2+	3D model available Symbol and footprint available 3	1 Download Model
	LAT-2+ Mini-Circuits	1	Attenuators 2 dB SMT Fixed Attenuator, DC - 2500 MHz, 50?	Other	LAT-2+	3D model available Symbol and footprint available 3	1 Download Model
	KAT-2+ Mini-Circuits	1	Attenuators 2 dB SMT Fixed Attenuator, DC - 43500 MHz, 50?	Small Outline No-lead	KAT-2+	3D model available Symbol and footprint available 3	1 Download Model
	HMC189AMS8E Analog Devices	1	ANALOG DEVICES - HMC189AMS8E - RF Passive Frequency Doubler IC, 2 GHz to 4 GHz Input, 13 dB Loss, MSOP-8	Small Outline Packages	HMC189AMS8E	3D model available Symbol and footprint available 3	1 Download Model
	HMC996LP4E Analog Devices	1	ANALOG DEVICES - HMC996LP4E - RF Amplifier, Variable, 16 dB Gain / 2 dB Noise, 5 GHz to 12 GHz, 5 V / 120 mA Supply, QFN-24	Quad Flat No-Lead	HMC996LP4E	3D model available Symbol and footprint available 3	1 Download Model
	TXA4-512HP+ Mini-Circuits	1	High input power, 5 Watt max. Low amplitude unbalance, 0.3 dB typ. Excellent phase unbalance, 2 deg. typ	Other	TXA4-512HP+	3D model available Symbol and footprint available 3	1 Download Model
	MAX2614ETA+T Analog Devices	1	MAXIM INTEGRATED / ANALOG DEVICES - MAX2614ETA+T - RF Amplifier, 18.6 dB Gain / 2 dB Noise, 40 MHz to 4 GHz, 3 V to 5.25 V Supply, TDFN-8	Small Outline No-lead	MAX2614ETA+T	3D model available Symbol and footprint available 3	1 Download Model
	AMT-32+ Mini-Circuits	1	low insertion S-1 and S-2, 0.5 dB typ; J-1 and J-2, 0.5 dB typ. very good input VSWR, 1.3 typ. and good output VSWR, 1.35 typ. excellent amplitude unbalance, 0.2 dB typ. excellent phase unbalance, 2 deg. typ. high isolation S-J ports and 1-2 ports, 35 dB typ. protected under US Patent 6,133,525	Other	AMT-32+	3D model available Symbol and footprint available 3	1 Download Model
	HA17741 HITACHI	1	High voltage gain : 106 dB (Typ) • Wide output amplitude : ±13 V (Typ) (at RL ≥ 2 kΩ) • Shorted output protection • Adjustable offset voltage	Dual-In-Line Packages	HA17741	3D model available Symbol and footprint available 3	1 Download Model
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