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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V255LA15TFGI Renesas Electronics	1	The 72V255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72255 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that nee	Quad Flat Packages	72V255LA15TFGI	3D model available Symbol and footprint available 3	1 Download Model
	7203L12JG Renesas Electronics	1	The 7203 is a 2K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7203L12JG	3D model not available Symbol and footprint available 2	1 Download Model
	72T18105L5BB Renesas Electronics	1	The 72T18105 is a 128K x 18 / 256K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18105L5BB	3D model available Symbol and footprint available 3	1 Download Model
	7283L12PAG Renesas Electronics	1	The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7283L12PAG	3D model available Symbol and footprint available 3	1 Download Model

	72V231L15PFGI8 Renesas Electronics	1	The 72V231 is a 2K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72231 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V231L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V285L15PFGI Renesas Electronics	1	IC MEM FIFO 65536X18 64-TQFP	Quad Flat Packages	72V285L15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7881-15PN Texas Instruments	1	FIFO 1024 x 18 synch FIFO Memory	Quad Flat Packages	SN74ACT7881-15PN	3D model available Symbol and footprint available 3	1 Download Model
	CD40105BE Texas Instruments	1	CMOS 4-Bit-by-16-Word FIFO Register	Dual-In-Line Packages	CD40105BE	3D model available Symbol and footprint available 3	1 Download Model
	SN74V273-10GGM Texas Instruments	1	FIFO 16K X 18, SYNCHRONOUS FIFO	BGA	SN74V273-10GGM	3D model available Symbol and footprint available 3	1 Download Model
	SN74ABT7820-25PH Texas Instruments	1	FIFO 512 x 18 x 2 bidir ASynch FIFO Memory	Quad Flat Packages	SN74ABT7820-25PH	3D model available Symbol and footprint available 3	1 Download Model
	CD74HC40105E Texas Instruments	1	High Speed CMOS Logic 4-Bit by 16-Word FIFO Register	Dual-In-Line Packages	CD74HC40105E	3D model available Symbol and footprint available 3	1 Download Model
	72V273L6PFG8 Renesas Electronics	1	FIFO, 16KX18, 4ns, Synchronous, CMOS, PQFP80	Quad Flat Packages	72V273L6PFG8	3D model available Symbol and footprint available 3	1 Download Model
	SN74V273-7GGM Texas Instruments	1	FIFO 16384 x 18 Synch FIFO Memory	BGA	SN74V273-7GGM	3D model available Symbol and footprint available 3	1 Download Model
	72V225L10TFG8 Renesas Electronics	1	FIFO, 1KX18, 6.5ns, Synchronous, CMOS, PQFP64	Quad Flat Packages	72V225L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	SN74ALVC7804-40DL Texas Instruments	1	SN74ALVC7804-40DL, FIFO Memory Dual 512 x 18 Uni-Directional 18ns 25MHz 3.3V 56-Pin SSOP	Small Outline Packages	SN74ALVC7804-40DL	3D model available Symbol and footprint available 3	1 Download Model

	CD74HCT40105M Texas Instruments	1	High Speed CMOS Logic 4-Bit by 16-Word FIFO Register	Small Outline Packages	CD74HCT40105M	3D model available Symbol and footprint available 3	1 Download Model
	SN74ALVC7804-25DL Texas Instruments	1	512 x 18 3.3-V asynchronous FIFO memory	Small Outline Packages	SN74ALVC7804-25DL	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7814-20DL Texas Instruments	1	SN74ACT7814-20DL, FIFO Memory Dual 1.125kbit 64 x 18 bit Uni-Directional 15ns 50MHz 4.5 → 5.5 V 56-Pin SSOP	Small Outline Packages	SN74ACT7814-20DL	3D model available Symbol and footprint available 3	1 Download Model
	CD74HCT40105EE4 Texas Instruments	1	FIFO Register Single 4-CH CMOS 16-Pin PDIP Tube	Dual-In-Line Packages	CD74HCT40105EE4	3D model available Symbol and footprint available 3	1 Download Model
	SN74V225-7PAG Texas Instruments	1	SN74V225-7PAG, FIFO Memory Dual 1K x 18 bit Uni-Directional 5ns 133MHz 3.3V 64-Pin TQFP	Quad Flat Packages	SN74V225-7PAG	3D model available Symbol and footprint available 3	1 Download Model
	CD74HC40105ME4 Texas Instruments	1	Registers 4bit x 16Word FIFO	Small Outline Packages	CD74HC40105ME4	3D model available Symbol and footprint available 3	1 Download Model
	M66288FP Renesas Electronics	1	MOTION ENCODER	Quad Flat Packages	M66288FP	3D model available Symbol and footprint available 3	1 Download Model
	72V2103L7-5BCI Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V2103L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model
	72215LB10PFG Renesas Electronics	1	The 72215 is a 512 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain techniqu	Quad Flat Packages	72215LB10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V233L7-5BC Renesas Electronics	1	The 72V233 2K x 9/1K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V233L7-5BC	3D model available Symbol and footprint available 3	1 Download Model
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