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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	70V658S15BC Renesas Electronics	1	The 70V658 is a high-speed 64K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	BGA	70V658S15BC	3D model not available Symbol and footprint available 2	1 Download Model
	71V016SA20PHGI8 Renesas Electronics	1	The 71V016 3.3V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Small Outline Packages	71V016SA20PHGI8	3D model available Symbol and footprint available 3	1 Download Model
	7008L20JGI Renesas Electronics	1	The 7008 is a high-speed 64K x 8 Dual-Port Static RAM designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Plastic Leaded Chip Carrier	7008L20JGI	3D model not available Symbol and footprint available 2	1 Download Model
	71V124SA12TYG Renesas Electronics	1	The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Small Outline Packages	71V124SA12TYG	3D model available Symbol and footprint available 3	1 Download Model

	5962-8700204ZA Renesas Electronics	1	The 5962-87002 (IDT 7132/42) is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with M	Ceramic Dual-In-Line Packages	5962-8700204ZA	3D model not available Symbol and footprint available 2	1 Download Model
	N01S830HAT22I onsemi	1	Power Supply Range: 2.5 to 5.5 V; Very Low Typical Standby Current: < 4 µA; Very Low Operating Current: < 10 mA; Simple Serial Interface - Single-bit SPI Access - DUAL-bit and QUAD-bit SPI-like Access; Flexible Operating Modes - Word Mode - Page Mode - Burst Mode (Full Array); High Frequency Read and Write Operation - Clock Frequency 20 MHz; Functional Options - HOLD Pin for Pausing Operation - VBAT Pin for Battery−Back up; Built-in Write Protection (CS High); High Reliability - Unlimited Write Cycles	Small Outline Packages	N01S830HAT22I	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S166PFG Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S166PFG	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S100BGI8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S100BGI8	3D model available Symbol and footprint available 3	1 Download Model
	70V3399S133BFI8 Renesas Electronics	1	The 70V3399 is a high-speed 128K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3399 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	BGA	70V3399S133BFI8	3D model available Symbol and footprint available 3	1 Download Model
	71256L55TDB Renesas Electronics	1	The 71256 5V CMOS SRAM is organized as 32K x 8. The circuit also offers a reduced power standby mode for significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability allowing operation off a 2V battery. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	71256L55TDB	3D model not available Symbol and footprint available 2	1 Download Model
	70V3319S166PRFG8 Renesas Electronics	1	The 70V3319 is a high-speed 256K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3319 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	Quad Flat Packages	70V3319S166PRFG8	3D model available Symbol and footprint available 3	1 Download Model
	70V7519S133BF8 Renesas Electronics	1	The 70V7519 is a high-speed 256K x 36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70V7519S133BF8	3D model available Symbol and footprint available 3	1 Download Model
	70T3719MS166BBG Renesas Electronics	1	The 70T3719M is a high-speed 256K x 72 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3719M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3719MS166BBG	3D model available Symbol and footprint available 3	1 Download Model
	M48T512Y-70PM1 STMicroelectronics	1	Real Time Clock (RTC) IC Clock/Calendar Parallel 32-DIP Module (0.600", 15.24mm),0°C ~ 70°C,Through Hole,4.5V ~ 5.5V,4mA	Other	M48T512Y-70PM1	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S150PFG Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S150PFG	3D model available Symbol and footprint available 3	1 Download Model

	71421LA20PFG8 Renesas Electronics	1	The 71421 is a high-speed 2K x 8 Dual-Port Static RAM with internal interrupt logic for interprocessor communications. It is designed to be used as a "SLAVE" Dual-Port RAM together with the 71321 "MASTER" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	71421LA20PFG8	3D model available Symbol and footprint available 3	1 Download Model
	70T3319S133BC Renesas Electronics	1	The 70T3319 is a high-speed 256K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3319 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3319S133BC	3D model available Symbol and footprint available 3	1 Download Model
	5962-3829417MZA Renesas Electronics	1	The 5962-38294 (7164 SRAM) is organized as 8K x 8 and offers a reduced power standby mode. The low-power version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation.	Ceramic Dual-In-Line Packages	5962-3829417MZA	3D model not available Symbol and footprint available 2	1 Download Model
	7130SA35C Renesas Electronics	1	The 7130 is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535	Ceramic Dual-In-Line Packages	7130SA35C	3D model not available Symbol and footprint available 2	1 Download Model
	71T75602S150BGGI Renesas Electronics	1	The 71T75602 2.5V CMOS Synchronous SRAM organized as 512K x 36 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75602 contains data I/O, address and control signal registers.	BGA	71T75602S150BGGI	3D model available Symbol and footprint available 3	1 Download Model
	70V659S10BC Renesas Electronics	1	The 70V659 is a high-speed 128K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po	BGA	70V659S10BC	3D model available Symbol and footprint available 3	1 Download Model
	71V424L12PHG Renesas Electronics	1	The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Small Outline Packages	71V424L12PHG	3D model available Symbol and footprint available 3	1 Download Model
	70T651S15BC Renesas Electronics	1	The 70T651 is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T651S15BC	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S133BG8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S133BG8	3D model available Symbol and footprint available 3	1 Download Model
	70V658S10BC Renesas Electronics	1	The 70V658 is a high-speed 64K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por	BGA	70V658S10BC	3D model available Symbol and footprint available 3	1 Download Model
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