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R1LP5256ESP-5SI#S0
Renesas Electronics
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1 | The R1LP5256E Series is a family of low voltage 256-Kbit static RAMs organized as 32, 768-word by 8-bit, fabricated by Renesas’s high-performance 0. 15um CMOS and TFT technologies. The R1LP5256E Series has realized higher density, higher performance and low power consumption. The R1LP5256E Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. It has been packaged in 28-pin SOP and 28-pin TSOP. | Small Outline Packages | R1LP5256ESP-5SI#S0 |
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70V3589S133DRGI8
Renesas Electronics
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1 | The 70V3589 is a high-speed 64K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3589 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V. | Quad Flat Packages | 70V3589S133DRGI8 |
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71V3577S85BQI8
Renesas Electronics
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1 | The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V3577S85BQI8 |
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71V2556SA100BGI
Renesas Electronics
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1 | The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V2556SA100BGI |
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709159L6BF
Renesas Electronics
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1 | The 709159 is a high-speed 8K x 9 bit synchronous Dual-Port SRAM that has been optimized for applications having unidirectional data flow or bi-directional data flow in bursts, by utilizing input data registers. The 709159 utilizes a 9-bit wide data path to allow for parity which is useful in data communication applications where it is necessary to use a parity bit for transmission/ reception error checking. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to ent | BGA | 709159L6BF |
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70V3579S4BF8
Renesas Electronics
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1 | The 70V3579 is a high-speed 32K × 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3579 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V. | BGA | 70V3579S4BF8 |
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5962-8687506XA
Renesas Electronics
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1 | The 5962-86875 (IDT 7130/40) is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with | Ceramic Dual-In-Line Packages | 5962-8687506XA |
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70V657S10BF
Renesas Electronics
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1 | The 70V657 is a high-speed 32K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each por | BGA | 70V657S10BF |
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71256SA15PZGI8
Renesas Electronics
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1 | The 71256SA 5V CMOS SRAM is organized as 32K x 8. All bidirectional inputs and outputs of the 71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. | Other | 71256SA15PZGI8 |
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7133SA35G
Renesas Electronics
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1 | The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available. | Other | 7133SA35G |
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71V3559S85PFG8
Renesas Electronics
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1 | The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3559 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). | Quad Flat Packages | 71V3559S85PFG8 |
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71V256SA12YGI
Renesas Electronics
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1 | The 71V256SA 3.3V CMOS Asynchronous SRAM is organized as 32K x 8. When in standby mode, its very low power characteristics contribute to extended battery life. Under full standby mode (CS at CMOS level, f=0), power consumption is guaranteed to be less than 6.6mW. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. | Other | 71V256SA12YGI |
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71V3577S85BQG8
Renesas Electronics
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1 | The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V3577S85BQG8 |
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70V3589S133BC
Renesas Electronics
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1 | The 70V3589 is a high-speed 64K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3589 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V. | BGA | 70V3589S133BC |
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70V7599S133BC8
Renesas Electronics
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1 | The 70V7599 is a high-speed 128K x 36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 2Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. | BGA | 70V7599S133BC8 |
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70T631S15BF8
Renesas Electronics
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1 | The 70T631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. | BGA | 70T631S15BF8 |
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70V3389S4BC
Renesas Electronics
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1 | The 70V3389 is a high-speed 64K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3389 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V. | BGA | 70V3389S4BC |
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70V35L15PFG
Renesas Electronics
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1 | The 70V35 is a high-speed 8K x 18 Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. | Quad Flat Packages | 70V35L15PFG |
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71V35761SA183BGG8
Renesas Electronics
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1 | The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V35761SA183BGG8 |
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HM1-65642/883
Renesas Electronics
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1 | The HM-65642/883 is a CMOS 8192 x 8-bit Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and RAMs. The HM-65642/883 is ideally suited for use in microprocessor based systems. In particular, interfacing with the Renesas 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input. The HM-65642/883 is a full CMOS RAM which utilizes an arra | Ceramic Dual-In-Line Packages | HM1-65642/883 |
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71V3556SA100BGI
Renesas Electronics
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1 | The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers. | BGA | 71V3556SA100BGI |
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7142LA20JG8
Renesas Electronics
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1 | The 7142 is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a "SLAVE" Dual-Port RAM together with the 7132 "MASTER" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available. | Plastic Leaded Chip Carrier | 7142LA20JG8 |
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71V67703S75PFGI8
Renesas Electronics
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1 | The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V67703S75PFGI8 |
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71V65903S85PFG8
Renesas Electronics
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1 | The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65903 contain address, data-in and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V65903S85PFG8 |
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70V659S10BFG
Renesas Electronics
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1 | The 70V659 is a high-speed 128K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po | BGA | 70V659S10BFG |
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