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70V3569S4BC
Renesas Electronics
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1 | The 70V3569 is a high-speed 16K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3569 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V. | BGA | 70V3569S4BC |
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71V65703S75PFG
Renesas Electronics
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1 | The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V65703S75PFG |
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71V546S133PFG
Renesas Electronics
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1 | The 71V546 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V546 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V546S133PFG |
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6116LA35DB
Renesas Electronics
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1 | The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available. | Dual-In-Line Packages | 6116LA35DB |
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71V67803S166PFGI8
Renesas Electronics
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1 | The 71V67803 3.3V CMOS SRAM is organized as 512K x 18. The 71V67803 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V67803S166PFGI8 |
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70V631S15BF8
Renesas Electronics
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1 | The 70V631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po | BGA | 70V631S15BF8 |
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70V3319S133BF
Renesas Electronics
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1 | The 70V3319 is a high-speed 256K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3319 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V. | BGA | 70V3319S133BF |
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R1Q4A4436RBG-33IB0
Renesas Electronics
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1 | The R1Q4A4436RBG is a 4, 194, 304-word by 36-bit and the R1Q4A4418RBG is a 8, 388, 608-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed, | BGA | R1Q4A4436RBG-33IB0 |
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7133LA20PFG8
Renesas Electronics
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1 | The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available. | Quad Flat Packages | 7133LA20PFG8 |
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5962-8687509XA
Renesas Electronics
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1 | The 5962-86875 (IDT 7130/40) is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with | Ceramic Dual-In-Line Packages | 5962-8687509XA |
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71V3559S85PFG8
Renesas Electronics
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1 | The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3559 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). | Quad Flat Packages | 71V3559S85PFG8 |
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71V3577S85BQG8
Renesas Electronics
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1 | The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V3577S85BQG8 |
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7140LA20JG
Renesas Electronics
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1 | The 7140 is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a "SLAVE" Dual-Port RAM together with the 7130 "MASTER" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available. | Plastic Leaded Chip Carrier | 7140LA20JG |
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71V65603S150BQGI8
Renesas Electronics
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1 | The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V65603S150BQGI8 |
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71V547S80PFG
Renesas Electronics
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1 | The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | Quad Flat Packages | 71V547S80PFG |
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7133SA35G
Renesas Electronics
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1 | The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available. | Other | 7133SA35G |
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71256SA15PZGI8
Renesas Electronics
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1 | The 71256SA 5V CMOS SRAM is organized as 32K x 8. All bidirectional inputs and outputs of the 71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. | Other | 71256SA15PZGI8 |
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70V3379S4PRFG
Renesas Electronics
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1 | The 70V3379 is a high-speed 32K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3379 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V. | Quad Flat Packages | 70V3379S4PRFG |
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7133LA25G
Renesas Electronics
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1 | The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available. | Other | 7133LA25G |
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70V9169L6PFG
Renesas Electronics
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1 | The 70V9169 is a high-speed 16K x 9 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. | Quad Flat Packages | 70V9169L6PFG |
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7008L20PFGI
Renesas Electronics
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1 | The 7008 is a high-speed 64K x 8 Dual-Port Static RAM designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. | Quad Flat Packages | 7008L20PFGI |
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70T653MS12BCGI
Renesas Electronics
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1 | The 70T653M is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone 18874K-bit Dual-Port RAM. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. | BGA | 70T653MS12BCGI |
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71V2546S133BG8
Renesas Electronics
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1 | The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. | BGA | 71V2546S133BG8 |
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R1LV0108ESN-5SI#B0
Renesas Electronics
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1 | The R1LV0108E Series is a family of low voltage 1-Mbit static RAMs organized as 131, 072-word by 8-bit, fabricated by Renesas’s high-performance 0. 15um CMOS and TFT technologies. The R1LV0108E Series has realized higher density, higher performance and low power consumption. The R1LV0108E Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. It has been packaged in 32-pin SOP, 32-pin TSOP and 32-pin sTSOP. | Small Outline Packages | R1LV0108ESN-5SI#B0 |
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R1QBA7236ABG-20IA0
Renesas Electronics
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1 | Support is limited to customers who have already adopted these products.DDR II / II+ (Double Data Rate) SRAMs and QDR^(TM) II / II+ (Quad Data Rate) SRAMs are the ideal memory devices for next generation networking and communications systems. These ultra-fast devices can support high bandwidth systems that require memories capable of very high operating frequencies combined with low latencies and full cycle utilization. DDR SRAMs can provide double data rate (DDR) operation on each data pin in write or read | BGA | R1QBA7236ABG-20IA0 |
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