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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71V67703S75PFGI8 Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67703S75PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	70V9169L6PFG Renesas Electronics	1	The 70V9169 is a high-speed 16K x 9 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	70V9169L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S133BG8 Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2546S133BG8	3D model available Symbol and footprint available 3	1 Download Model
	71V35761SA166BQG Renesas Electronics	1	The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM.	BGA	71V35761SA166BQG	3D model available Symbol and footprint available 3	1 Download Model

	71V3559S85BGI8 Renesas Electronics	1	The 71V3559 3.3V CMOS Synchronous SRAM is organized as 256K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3559 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).	BGA	71V3559S85BGI8	3D model available Symbol and footprint available 3	1 Download Model
	70T3519S200BCG Renesas Electronics	1	The 70T3519 is a high-speed 256K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3519 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3519S200BCG	3D model available Symbol and footprint available 3	1 Download Model
	70T653MS12BCGI Renesas Electronics	1	The 70T653M is a high-speed 256K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone 18874K-bit Dual-Port RAM. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T653MS12BCGI	3D model available Symbol and footprint available 3	1 Download Model
	709099L9PFGI Renesas Electronics	1	The 709099 is a high-speed 128K x 8 bit synchronous Dual- Port RAM. Registers on control, data, and address inputs provide minimal setup and hold times allowing systems to be designed with very short cycle times. With an input data register, it has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	709099L9PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V256SA12YGI Renesas Electronics	1	The 71V256SA 3.3V CMOS Asynchronous SRAM is organized as 32K x 8. When in standby mode, its very low power characteristics contribute to extended battery life. Under full standby mode (CS at CMOS level, f=0), power consumption is guaranteed to be less than 6.6mW. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71V256SA12YGI	3D model available Symbol and footprint available 3	1 Download Model
	7133LA25G Renesas Electronics	1	The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7133LA25G	3D model available Symbol and footprint available 3	1 Download Model
	7006L17G Renesas Electronics	1	The 7006 is a high-speed 16K x 8 Dual-Port Static RAM designed to be used as a stand-alone 128K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7006L17G	3D model available Symbol and footprint available 3	1 Download Model
	R1Q2A4436RBG-40IB0 Renesas Electronics	1	The R1Q2A4436RBG is a 4, 194, 304-word by 36-bit and the R1Q2A4418RBG is a 8, 388, 608-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed,	BGA	R1Q2A4436RBG-40IB0	3D model available Symbol and footprint available 3	1 Download Model
	71V124SA15PHGI Renesas Electronics	1	The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Small Outline Packages	71V124SA15PHGI	3D model available Symbol and footprint available 3	1 Download Model
	71V65903S80BQ Renesas Electronics	1	The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65903 contain address, data-in and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65903S80BQ	3D model available Symbol and footprint available 3	1 Download Model
	5962-8700212ZA Renesas Electronics	1	The 5962-87002 (IDT 7132/42) is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with M	Ceramic Dual-In-Line Packages	5962-8700212ZA	3D model not available Symbol and footprint available 2	1 Download Model

	71V35761S166PFG8 Renesas Electronics	1	The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V35761S166PFG8	3D model available Symbol and footprint available 3	1 Download Model
	M48T35Y-70MH6E STMicroelectronics	1	5 V, 256 Kbit (32 Kb x 8) TIMEKEEPERÂ® SRAM	Small Outline Packages	M48T35Y-70MH6E	3D model available Symbol and footprint available 3	1 Download Model
	71T75902S75PFGI Renesas Electronics	1	The 71T75902 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround.	Quad Flat Packages	71T75902S75PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V67602S166BGG8 Renesas Electronics	1	The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V67602S166BGG8	3D model available Symbol and footprint available 3	1 Download Model
	71T75802S200BGG Renesas Electronics	1	The 71T75802 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71T75802 contains data I/O, address and control signal registers.	BGA	71T75802S200BGG	3D model available Symbol and footprint available 3	1 Download Model
	71016S15YGI8 Renesas Electronics	1	The 71016 5V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71016 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71016S15YGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V3577S85BQI8 Renesas Electronics	1	The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V3577S85BQI8	3D model available Symbol and footprint available 3	1 Download Model
	71V416S15PHG8 Renesas Electronics	1	The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Small Outline Packages	71V416S15PHG8	3D model available Symbol and footprint available 3	1 Download Model
	70V3589S133BC Renesas Electronics	1	The 70V3589 is a high-speed 64K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3589 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 3.3V.	BGA	70V3589S133BC	3D model available Symbol and footprint available 3	1 Download Model
	71V547S80PFG Renesas Electronics	1	The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V547S80PFG	3D model available Symbol and footprint available 3	1 Download Model
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