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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71V424L12PHGI Renesas Electronics	1	The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Small Outline Packages	71V424L12PHGI	3D model available Symbol and footprint available 3	1 Download Model
	71V3577S75PFGI8 Renesas Electronics	1	The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V3577S75PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V3577S75BQI Renesas Electronics	1	The 71V3577 3.3V CMOS SRAM is organized as 128K x 36. The 71V3577 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V3577S75BQI	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S100BQI Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S100BQI	3D model available Symbol and footprint available 3	1 Download Model

	71V65803S150BQI8 Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S150BQI8	3D model available Symbol and footprint available 3	1 Download Model
	71V65703S85PFG8 Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65703S85PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V67602S166PFG8 Renesas Electronics	1	The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V67602S166PFG8	3D model available Symbol and footprint available 3	1 Download Model
	5962-8687513XA Renesas Electronics	1	The 5962-86875 (IDT 7130/40) is a high-speed 1K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with	Ceramic Dual-In-Line Packages	5962-8687513XA	3D model not available Symbol and footprint available 2	1 Download Model
	6116SA150TDB Renesas Electronics	1	The 6116 5V CMOS SRAM is organized as 2K x 8. The 6116 offers a reduced power standby mode.The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1μW to 4μW operating off a 2V battery. All inputs and outputs are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. Military grade product is available.	Ceramic Dual-In-Line Packages	6116SA150TDB	3D model not available Symbol and footprint available 2	1 Download Model
	7142SA55CB Renesas Electronics	1	The 7142 is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a "SLAVE" Dual-Port RAM together with the 7132 "MASTER" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.	Ceramic Dual-In-Line Packages	7142SA55CB	3D model not available Symbol and footprint available 2	1 Download Model
	7008S35G Renesas Electronics	1	The 7008 is a high-speed 64K x 8 Dual-Port Static RAM designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.	Other	7008S35G	3D model available Symbol and footprint available 3	1 Download Model
	71V424L12YGI Renesas Electronics	1	The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71V424L12YGI	3D model available Symbol and footprint available 3	1 Download Model
	71V124SA15TYGI Renesas Electronics	1	The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71V124SA15TYGI	3D model available Symbol and footprint available 3	1 Download Model
	M48T08Y-10MH1F STMicroelectronics	1	5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM	Small Outline Packages	M48T08Y-10MH1F	3D model available Symbol and footprint available 3	1 Download Model
	71V67703S75BGGI8 Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V67703S75BGGI8	3D model available Symbol and footprint available 3	1 Download Model

	70T631S12BFI Renesas Electronics	1	The 70T631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T631S12BFI	3D model available Symbol and footprint available 3	1 Download Model
	71V124SA10PHG Renesas Electronics	1	The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Small Outline Packages	71V124SA10PHG	3D model available Symbol and footprint available 3	1 Download Model
	CY14V116N-BZ30XI Infineon	1	NVRAM Non Volatile SRAMs	BGA	CY14V116N-BZ30XI	3D model available Symbol and footprint available 3	1 Download Model
	CY62148G-45ZSXI Infineon	1	SRAM MoBL SRAM 4-Mbit	Small Outline Packages	CY62148G-45ZSXI	3D model available Symbol and footprint available 3	1 Download Model
	IS64WV204816BLL-12CTLA3 Integrated Silicon Solution Inc.	1	SRAM 32Mb,High-Speed-Automotive,Async,2048K x 16,12ns,2.4v-3.6v,48 Pin TSOP I, RoHS, Automotive temp	Small Outline Packages	IS64WV204816BLL-12CTLA3	3D model available Symbol and footprint available 3	1 Download Model
	CY7C1470V33-200BZI Infineon	1	SRAM Chip Sync Quad 3.3V 72M-bit 2M x 36 3ns 165-Pin FBGA Tray	BGA	CY7C1470V33-200BZI	3D model available Symbol and footprint available 3	1 Download Model
	U62256AS2C07LLG1 Alliance Memory	1	SRAM,256K,32Kx8,70ns,5V,Low Power,SOP28 Alliance Memory U62256AS2C07LLG1 SRAM Memory, 256kbit, 3.3 → 5 V, 56ns 28-Pin SOP	Small Outline Packages	U62256AS2C07LLG1	3D model available Symbol and footprint available 3	1 Download Model
	CY14B101Q2A-SXI Infineon	1	NVRAM NVSRAM Serial-SPI 1Mbit 3.3V 8-Pin SOIC Tube	Small Outline Packages	CY14B101Q2A-SXI	3D model available Symbol and footprint available 3	1 Download Model
	CY7C2263KV18-450BZXI Infineon	1	SRAM Chip Sync Dual 1.8V 36M-bit 2M x 18 0.45ns 165-Pin FBGA Tray	BGA	CY7C2263KV18-450BZXI	3D model available Symbol and footprint available 3	1 Download Model
	IS62WV1288BLL-55TLI Integrated Silicon Solution Inc.	1	ISSI, IS62WV1288BLL-55TLI SRAM Memory, 1Mbit, 55ns, 2.5 → 3.6 V 32-Pin TSOP	Small Outline Packages	IS62WV1288BLL-55TLI	3D model available Symbol and footprint available 3	1 Download Model
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