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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	552-02SCMGI8 Renesas Electronics	1	The 552-02S is a low skew, single-input to eight-output clock buffer. The device offers a dual input with pin select for switching between two clock sources. It has best in class Additive Phase Jitter of sub 50 fsec.	Quad Flat No-Lead	552-02SCMGI8	3D model available Symbol and footprint available 3	1 Download Model
	85108AGILF Renesas Electronics	1	The 85108I is a low skew, high performance 1-to-8 Differential-to-0.7V HCSL Clock Distribution Chip. The 85108I CLK, nCLK pair can accept most differential input levels and translates them to 3.3V HCSL output levels. The 85108I provides a low power, low noise, low skew, point-to-point solution for distributing HCSL clock signals. Guaranteed output and part-to-part skew specifications make the 85108I ideal for those applications demanding well defined performance and repeatability.	Small Outline Packages	85108AGILF	3D model available Symbol and footprint available 3	1 Download Model
	9DBL0453ANLGI8 Renesas Electronics	1	The 9DBL0453 Zero-Delay/Fanout buffer is a low-power high-performance member of Renesas' Full-Featured PCIe family. The buffer supports PCIe Gen1–5 and provides a Loss of Signal (LOS) indicator. The device is an easy upgrade from the 9DBL0452. For information regarding evaluation boards and material, please contact your local sales representative.	Quad Flat No-Lead	9DBL0453ANLGI8	3D model available Symbol and footprint available 3	1 Download Model
	23S05E-1DCGI Renesas Electronics	1	3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible	Small Outline Packages	23S05E-1DCGI	3D model available Symbol and footprint available 3	1 Download Model

	8P34S2106AHGI Renesas Electronics	1	The 8P34S2106 is a high-performance, low-power, differential dual 1:6 LVDS output 1.8V / 2.5V fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Two independent buffer channels are available, each channel has six low-skew outputs. High isolation between channels minimizes noise coupling. AC characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew characteristics make th	BGA	8P34S2106AHGI	3D model available Symbol and footprint available 3	1 Download Model
	8545AG-02LF Renesas Electronics	1	The 8545-02 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS) the 8545-02 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The 8545-02 accepts an LVCMOS/LVTTL input level and translates it to 3.3V LVDS output levels. Guaranteed output and part-to-part skew characteristics make the 8545-02 ideal	Small Outline Packages	8545AG-02LF	3D model available Symbol and footprint available 3	1 Download Model
	8735BKI-21LF Renesas Electronics	1	The 8735BI-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL clock generator. The CLK, nCLK pair can accept most standard differential input levels. The 8735BI-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The referencedivider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The ex	Quad Flat No-Lead	8735BKI-21LF	3D model available Symbol and footprint available 3	1 Download Model
	NB7L14MN1TWG onsemi	1	Maximum Input Clock Frequnecy up to 7 GHz Typical; Maximum Input Data Rate up to 10 Gb/s Typical; < 0.8 ps of RMS Clock Jitter; < 15 ps of Data Dependent Jitter; 45 ps Typical Rise and Fall Times; 165 ps Typical Propogation Delay; 3 ps Typical Within Device Skew; Operating Range: VCC = 2.375 V to 3.6 V; LVPECL Output Level, 720 mV Peak-to-Peak; 50-ohm Internal Input Termination Resistors; Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG devices	Quad Flat No-Lead	NB7L14MN1TWG	3D model available Symbol and footprint available 3	1 Download Model
	CSPT855PGG Renesas Electronics	1	2.5V 1 to 4 differential clock distributor. Optimized for clock distribution in DDR SDRAM applications. Operating frequency: 60MHZ to 220MHz	Small Outline Packages	CSPT855PGG	3D model available Symbol and footprint available 3	1 Download Model
	74FCT807CTPYG Renesas Electronics	1	The FCT807T clock driver is built using advanced dual metal CMOS technology. This low skew clock driver features 1:10 fanout, providing minimal loading on the preceding drivers. The FCT807T offers low capacitance inputs with hysteresis for improved noise margins. TTL level outputs and multiple power and grounds reduce noise. The device also features -32/48mA drive capability for driving low impedance traces.	Small Outline Packages	74FCT807CTPYG	3D model available Symbol and footprint available 3	1 Download Model
	9DBU0931AKLFT Renesas Electronics	1	The 9DBU0931 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. The device has 5 output enables for clock management, and 3 selectable SMBus addresses.	Quad Flat No-Lead	9DBU0931AKLFT	3D model available Symbol and footprint available 3	1 Download Model
	853S006AGILF Renesas Electronics	1	The 853S006I is a low skew, high performance 1-to-6 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The 853S006I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 853S006I ideal for those clock distribution applications demanding well defined performance and repeatability.	Small Outline Packages	853S006AGILF	3D model available Symbol and footprint available 3	1 Download Model
	8533AGI-01LFT Renesas Electronics	1	The 8533I-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer. The 8533I-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8533I-01 ideal fo	Small Outline Packages	8533AGI-01LFT	3D model available Symbol and footprint available 3	1 Download Model
	74FCT3807ASOGI Renesas Electronics	1	The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS technology. This low skew clock driver offers 1:10 fanout. The large fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. The FCT3807/A offers low capacitance inputs with hysteresis for improved noise margins. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution.	Small Outline Packages	74FCT3807ASOGI	3D model available Symbol and footprint available 3	1 Download Model
	9DBV0531AKLFT Renesas Electronics	1	The 9DBV0531is a member of IDT's Full-Featured PCIe family. The device has 5 output enables for clock management, and 3 selectable SMBus addresses.	Quad Flat No-Lead	9DBV0531AKLFT	3D model available Symbol and footprint available 3	1 Download Model

	85304AGI-01LF Renesas Electronics	1	The ICS85304I-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout buffer. The ICS85304I-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept moststandard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin.Guaranteed output and part-to-part skew characteristics make the ICS85304I-01 ideal for those applications demanding well defined per	Small Outline Packages	85304AGI-01LF	3D model available Symbol and footprint available 3	1 Download Model
	854S202AYILF Renesas Electronics	1	The 854S202I is a 12:2 Differential-to-LVDS Clock Multiplexer which can operate >3GHz. The 854S202I has 12 selectable differential clock inputs, any of which can be independently routed to either of the two LVDS outputs. The CLKx, nCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.	Quad Flat Packages	854S202AYILF	3D model available Symbol and footprint available 3	1 Download Model
	23S08-1HDCG Renesas Electronics	1	SOIC 150 MIL	Small Outline Packages	23S08-1HDCG	3D model not available Symbol and footprint available 2	1 Download Model
	49FCT3805ASOGI8 Renesas Electronics	1	The FCT3805 is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805 offers low capacitance inputs with hysteresis. The FCT3805 is designed for high speed clock distribution where si	Small Outline Packages	49FCT3805ASOGI8	3D model available Symbol and footprint available 3	1 Download Model
	9DB433AFLFT Renesas Electronics	1	The 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.	Small Outline Packages	9DB433AFLFT	3D model available Symbol and footprint available 3	1 Download Model
	23S09-1DCGI Renesas Electronics	1	The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device.	Small Outline Packages	23S09-1DCGI	3D model available Symbol and footprint available 3	1 Download Model
	6T39007ANLGI8 Renesas Electronics	1	The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 V LVCMOS input and generates four high-quality LVDS outputs, and two programmable divided outputs. It includes a redundant input with automatic glitch-free switching when the primary reference is removed. The primary input may be selected by the user by pulling the SEL pin low or high. If the primary input is removed and brought back, it will not be re-selected until 1024 cycles have passed. The I	Quad Flat No-Lead	6T39007ANLGI8	3D model available Symbol and footprint available 3	1 Download Model
	9DBL0751BKILFT Renesas Electronics	1	The 9DBL0751 device is a member of IDT's 3.3V full-featured PCIe clock family. The 9DBL0751 device supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. The device's integrated output terminations provide a direct connection to 85Ω transmission lines. The 9DBL07P1 can be factory programmed with a user-defined power up default SMBus configuration.For information regarding evaluation boards and material, please contact your local IDT sales representative.	Quad Flat No-Lead	9DBL0751BKILFT	3D model available Symbol and footprint available 3	1 Download Model
	RC19004AGNL#KB0 Renesas Electronics	1	The RC19004 is a 4-output PCIe Gen6 buffer that is backward compatible with earlier PCIe generations. The RC19004 provides ultra-low additive jitter and reduced in-to-out delay performance for better design margin and incorporates several features for easier and more robust design.	Quad Flat No-Lead	RC19004AGNL#KB0	3D model available Symbol and footprint available 3	1 Download Model
	23S09-1HDCGI8 Renesas Electronics	1	The IDT23S09 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT23S09 is a 16-pin version of the IDT23S05. The IDT23S09accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device.	Small Outline Packages	23S09-1HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
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