Other Footprint, Symbol and 3D Model search results

Showing 25 of 33685 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72201L10JG Renesas Electronics	1	The 72201SyncFIFO™ is a 256 x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Plastic Leaded Chip Carrier	72201L10JG	3D model not available Symbol and footprint available 2	1 Download Model
	72T1855L6-7BB Renesas Electronics	1	The 72T1855 is a 4K x 18 / 8K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1855L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72T1875L6-7BB Renesas Electronics	1	The 72T1875 is a 16K x 18 / 32K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1875L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72265LA10PFG Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA10PFG	3D model available Symbol and footprint available 3	1 Download Model

	72V223L6BC Renesas Electronics	1	The 72V223 1K x 9/512 x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V223L6BC	3D model available Symbol and footprint available 3	1 Download Model
	72285L10PFG Renesas Electronics	1	The 72285 is a 64K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72285L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V285L10PFG8 Renesas Electronics	1	The 72V285 is an 64K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72285 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V285L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V225L10TFG Renesas Electronics	1	The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V225L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	7206L20DB Renesas Electronics	1	The 7206 is a 16K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7206L20DB	3D model not available Symbol and footprint available 2	1 Download Model
	72V273L6PFG Renesas Electronics	1	The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V273L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V06L15JG Renesas Electronics	1	The 72V06 is a 16K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V06L15JG	3D model available Symbol and footprint available 3	1 Download Model
	72265LA10TFG Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72V273L6BC Renesas Electronics	1	The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V273L6BC	3D model available Symbol and footprint available 3	1 Download Model
	7202LA15PDGI Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7202LA15PDGI	3D model not available Symbol and footprint available 2	1 Download Model
	72V273L7-5BCI Renesas Electronics	1	The 72V273 32K x 9/16K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V273L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model

	72V3611L15PFG Renesas Electronics	1	The 72V3611 is a 64 x 36 3.3V Sync FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Communication between each port can take place through two 36-bit mailbox registers. Two or more devices may be used in parallel to create wider data paths. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with	Quad Flat Packages	72V3611L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V285L10TFG8 Renesas Electronics	1	The 72V285 is an 64K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72285 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V285L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V3680L6PFG8 Renesas Electronics	1	The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3680L6PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72T18105L5BBI Renesas Electronics	1	The 72T18105 is a 128K x 18 / 256K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18105L5BBI	3D model available Symbol and footprint available 3	1 Download Model
	72231L10JG Renesas Electronics	1	The 72231SyncFIFO™ is a 2K x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Plastic Leaded Chip Carrier	72231L10JG	3D model not available Symbol and footprint available 2	1 Download Model
	72221L15JGI8 Renesas Electronics	1	The 72221SyncFIFO™ is a 1K x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Plastic Leaded Chip Carrier	72221L15JGI8	3D model not available Symbol and footprint available 2	1 Download Model
	72V235L15TFGI8 Renesas Electronics	1	The 72V235 is a 2K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72235 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V235L15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V241L10PFG Renesas Electronics	1	The 72V241 is a 4K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72241 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V241L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72211L10PFG8 Renesas Electronics	1	The 72211SyncFIFO™ is a 512 x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72211L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72T36125L10BB Renesas Electronics	1	The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36125L10BB	3D model available Symbol and footprint available 3	1 Download Model
3 4 5 6 7 8 9 10 11

Can't find what you're looking for? Request this part

Other Model Download Search Results

Popular FIFOs