2364- Model Download Search Results
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236-441
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 41-pole; CAGE CLAMP®; commoning option | Other | 236-441 |
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236-408/332-000
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 8-pole; CAGE CLAMP®; commoning option | Other | 236-408/332-000 |
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 2-pole; suitable for Ex-e applications; CAGE CLAMP®; commoning option | Other | 236-402/332-009/999-950 |
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236-402/000-005
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 2-pole; CAGE CLAMP®; commoning option | Other | 236-402/000-005 |
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PE423641MLAA-Z
Peregrine Semiconductor
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1 | RF Switch ICs AEC-Q100 Certified SP4T, Low IL, Reflective, 50? RF Switch | Quad Flat No-Lead | PE423641MLAA-Z |
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236-404/334-604
Wago
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1 | THR PCB terminal block; 2.5 mm²; Pin spacing 5 mm; 4-pole; CAGE CLAMP®; commoning option | Other | 236-404/334-604 |
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236-448
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 48-pole; CAGE CLAMP®; commoning option | Other | 236-448 |
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236-409/334-604
Wago
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1 | THR PCB terminal block; 2.5 mm²; Pin spacing 5 mm; 9-pole; CAGE CLAMP®; commoning option | Other | 236-409/334-604 |
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236-436
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 36-pole; CAGE CLAMP®; commoning option | Other | 236-436 |
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236-419
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 19-pole; CAGE CLAMP®; commoning option | Other | 236-419 |
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236-402/332-000
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 2-pole; CAGE CLAMP®; commoning option | Other | 236-402/332-000 |
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236-403
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 3-pole; CAGE CLAMP®; commoning option | Other | 236-403 |
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 4-pole; suitable for Ex-e applications; CAGE CLAMP®; commoning option | Other | 236-404/332-009/999-950 |
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236-401/332-000
Wago
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1 | Stackable PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 1-pole; CAGE CLAMP®; commoning option | Other | 236-401/332-000 |
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236-410
Wago
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1 | PCB terminal block; 2.5 mm²; Pin spacing 5/5.08 mm; 10-pole; CAGE CLAMP®; commoning option | Other | 236-410 |
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232-364
Wago
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1 | THT male header for double-deck assembly; 1.0 x 1.0 mm solder pin; angled; Pin spacing 5.08 mm; 4-pole | Other | 232-364 |
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832-3643
Wago
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1 | THT male header; 1.2 x 1.2 mm solder pin; angled; 100% protected against mismating; Silver-plated contacts; Pin spacing 10.16 mm; 3-pole | Other | 832-3643 |
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OPA2364AIDGKTG4
Texas Instruments
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1 | Operational Amplifiers - Op Amps 1.8V High CMR RRIO Op Amp | Small Outline Packages | OPA2364AIDGKTG4 |
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OPA2364IDGKT
Texas Instruments
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1 | 1.8V, High CMR, RRIO Op Amp | Small Outline Packages | OPA2364IDGKT |
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OPA2364IDGKR
Texas Instruments
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1 | 1.8V, High CMR, RRIO Op Amp | Small Outline Packages | OPA2364IDGKR |
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2364030-1
TE Connectivity
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1 | 144 Position High Speed Backplane Connector, 9 Row, 16 Column, PCB Mount Receptacle, Vertical, Unshrouded, 1.8 mm Centerline | Other | 2364030-1 |
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2364427-1
TE Connectivity
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1 | Board-to-Board, 36 Position, 1 mm [.04 in] Centerline, Vertical, Black, 11.25 mm [.44 in] Height, 8.2 mm [.32 in] Width, PCI & PCI Express Connectors | Other | 2364427-1 |
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M20-7823646
Harwin
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1 | M20: 36 Pos Receptacle SIL Straight 3mm THT Connector 8.5mm high Tin | Other | M20-7823646 |
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723642L15PFG
Renesas Electronics
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1 | The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. | Quad Flat Packages | 723642L15PFG |
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723642L15PFG8
Renesas Electronics
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1 | The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. | Quad Flat Packages | 723642L15PFG8 |
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