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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	8SLVD1212ANLGI8 Renesas Electronics	1	The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	MK1575-01GILFTR Renesas Electronics	1	The MK1575-01 is a clock recovery Phase-Locked Loop (PLL) designed for clock synthesis and synchronization in cost sensitive applications. The device is optimized to accept a low-frequency reference clock to generate a high-frequency data or graphics pixel clock. External loop filter components allow tailoring of loop frequency response characteristics. For low jitter / phase noise requirements refer to the MK2069 products.	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	527R-03LFT Renesas Electronics	1	The 527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The 527-03 aligns rising edges on CLKIN with FBPECL at a ratio determined by the referenc	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	9DBL0455NLGI8 Renesas Electronics	1	The device is a 4-output PCIe clock fanout buffers for PCIe Gen1–5 applications. It has an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock. For information regarding evaluation boards and material, please contact your local sales representative.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model

	9DMV0441AKILFT Renesas Electronics	1	The 9DMV0441 is a member of IDT's SOC-Friendly 1.8 V Very-Low-Power (VLP) PCIe Gen1-2-3 family. It has integrated output terminations providing Zo=100 ohms for direct connection to 100 ohm transmission lines. Each of the 4 outputs has its own dedicated OE# pin for optimal system control and power management. The part provides asynchronous and glitch-free switching modes.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	9DMU0141AKILF Renesas Electronics	1	The 9DMU0141 is a member of IDT's SOC-Friendly 1.5 V Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has integrated output terminations providing Zo=100 ohms for direct connection to 100 ohm transmission lines. The output has an OE# pin for optimal system control and power management. The part provides asynchronous or glitch-free switching modes.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	85211BMI-03LN Renesas Electronics	1	The 85211BI-03 is a low skew, high performance 1-to-2 Differential-to-LVHSTL Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The 85211BI-03 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 85211BI-03 ideal for those clock distribution applications demanding well defined performance and repeatability.	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	853S006AGILFT Renesas Electronics	1	The 853S006I is a low skew, high performance 1-to-6 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The 853S006I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 853S006I ideal for those clock distribution applications demanding well defined performance and repeatability.	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	851S201CKILF Renesas Electronics	1	The 851S201I is a high performance 2:2 Differential-to-HCSL Multiplexer with a 2 output fanout buffer. The 851S201I operates up to 250MHz and accepts HCSL and other low level differential inputs levels. Input level detection circuitry is available to flag input levels that drops below a specified value and on the selected input. This signal is latched until the status is reset via the alarm reset input. The 851S201I is packaged in a small 3 x 3 mm 16 lead VFQFN package, making it ideal for use on space cons	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	8SLVP1208ANBGI/W Renesas Electronics	1	The 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1208 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	870919BVILFT Renesas Electronics	1	The 870919I is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the selected reference clock. The device offers eight outputs. The PLL loop filter is completely internal and does not require external components. Several output configurations of the PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow applications to optimize frequency generation over a wide range of input reference frequencies. The PLL can also be	Plastic Leaded Chip Carrier	Check Price & Stock	3D model not available Symbol and footprint available 2	1 Download Model
	9DBU0531AKLF Renesas Electronics	1	The 9DBU0531 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. The device has 5 output enables for clock management, and 3 selectable SMBus addresses.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	9DBU0541AKILFT Renesas Electronics	1	The 9DBU0541 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 ohm transmission lines. The device has 5 output enables for clock management, and 3 selectable SMBus addresses.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	9DBL0853ANDGI8 Renesas Electronics	1	The 9DBL0853 Zero-Delay/Fanout buffer is a low-power high-performance member of Renesas' Full-Featured PCIe family. The buffer supports PCIe Gen1–5 and provides a Loss of Signal (LOS) indicator. The device is an easy upgrade from the 9DBL0851. For information regarding evaluation boards and material, please contact your local sales representative.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	854S036AKLFT Renesas Electronics	1	The 854S036 is a low skew, high performance Dual Differential-to-LVDS Fanout Buffer. One of the two fanout buffers has 3 LVDS outputs, the other has 6 LVDS outputs. The PCLKx, nPCLKx pairs can accept most standard differential input levels. The 854S036 is characterized to operate from a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S036 ideal for those clock distribution applications demanding well defined performance and repeatability.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model

	663MILF Renesas Electronics	1	The IDT663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the IDT674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies. The phase detector and VCO functions of the device can also be used independently. This enables the config	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	MPC962305EF-1H Renesas Electronics	1	The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	9P960AFLF Renesas Electronics	1	Dual Channel DDRII/III Zero Delay Buffer	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	2309NZ-1HDCG8 Renesas Electronics	1	The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback to a PLL. The IDT2309NZ operates at 3.3V and outputs can run up to 133.33MHz The IDT2309NZ is designed for low EMI and power optimization. It has multiple VDD and VSS pins for noise optimization and consumes less than 32mA at 66	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	551SDCGI8 Renesas Electronics	1	The 551S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 551S has best in class Additive Phase Jitter of sub 50 fsec.	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	8S58035AKILF Renesas Electronics	1	The 8S58035I is a high speed 2-to-6 Differential-to-LVPECL Fanout Buffer. The 8S58035I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel. The internally terminated differential inputs and VREF_AC pins allow other differential signal families such as LVDS, LVDS and CML to be easily interfaced to the input with minimal use of external components. The device also has a 2:1 MUX input, al	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	RC19016A100GN1#KB0 Renesas Electronics	1	The RC19016 is a 16-output PCIe Gen6 buffer that is backward compatible to earlier PCIe generations. The RC19016 provides ultra-low additive jitter and reduced in-to-out delay performance for better design-margin and incorporates several features for easier and more robust design.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	9DMV0131BKILFT Renesas Electronics	1	The 9DMV0131 is a member of Renesas' SOC-Friendly 1.8 V Very-Low-Power (VLP) PCIe Gen1–5 family. The output has an OE# pin for optimal system control and power management. The part provides asynchronous or glitch-free switching modes.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	2308B-1DCGI Renesas Electronics	1	The 2308B is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308B has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
	9ZXL1530BKLF Renesas Electronics	1	The 9ZXL1530 is a low-power version of the 9ZX21501. It has 15 low-power HCSL-compatible outputs and meets all the performance requirements of the Intel DB1900Z specification, while reducing power consumption more than 50% from the original IDT9ZX21501. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.	Quad Flat No-Lead	Check Price & Stock	3D model available Symbol and footprint available 3	1 Download Model
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