Clock Drivers Footprint, Symbol and 3D Model search results

Showing 25 of 2538 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	85411AMLF Renesas Electronics	1	The 85411 is a low skew, high performance 1-to-2 Differential-to-LVDS Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The 85411 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 85411 ideal for those clock distribution applications demanding well defined performance and repeatability.	Small Outline Packages	85411AMLF	3D model available Symbol and footprint available 3	1 Download Model
	8SLVP1208ANBGI/W Renesas Electronics	1	The 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1208 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are	Quad Flat No-Lead	8SLVP1208ANBGI/W	3D model available Symbol and footprint available 3	1 Download Model
	851S201CKILF Renesas Electronics	1	The 851S201I is a high performance 2:2 Differential-to-HCSL Multiplexer with a 2 output fanout buffer. The 851S201I operates up to 250MHz and accepts HCSL and other low level differential inputs levels. Input level detection circuitry is available to flag input levels that drops below a specified value and on the selected input. This signal is latched until the status is reset via the alarm reset input. The 851S201I is packaged in a small 3 x 3 mm 16 lead VFQFN package, making it ideal for use on space cons	Quad Flat No-Lead	851S201CKILF	3D model available Symbol and footprint available 3	1 Download Model
	23S05E-1DCGI Renesas Electronics	1	3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible	Small Outline Packages	23S05E-1DCGI	3D model available Symbol and footprint available 3	1 Download Model

	74FCT3807QGI Renesas Electronics	1	The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS technology. This low skew clock driver offers 1:10 fanout. The large fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. The FCT3807/A offers low capacitance inputs with hysteresis for improved noise margins. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution.	Small Outline Packages	74FCT3807QGI	3D model available Symbol and footprint available 3	1 Download Model
	874003AG-02LFT Renesas Electronics	1	The 874003-02 is a high performance Differential-to- LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874003-02 has a bandwidth of 400kHz which is d	Small Outline Packages	874003AG-02LFT	3D model available Symbol and footprint available 3	1 Download Model
	23S08E-2DCG Renesas Electronics	1	3.3V Zero Delay Clock Multiplier, Spread Spectrum Compatible	Small Outline Packages	23S08E-2DCG	3D model available Symbol and footprint available 3	1 Download Model
	23S08E-2DCGI8 Renesas Electronics	1	3.3V Zero Delay Clock Multiplier, Spread Spectrum Compatible	Small Outline Packages	23S08E-2DCGI8	3D model available Symbol and footprint available 3	1 Download Model
	8V79S674NLGI Renesas Electronics	1	The 8V79S674 is a clock divider and fanout buffer. The device has been designed for clock signal division in wireless base station radio equipment boards. The device is optimized to deliver excellent additive phase jitter performance. The 8V79S674 uses SiGe technology for an optimum of high clock frequency and low phase noise performance, combined with high power supply noise rejection. The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four low-skew LVPECL outputs are available and support cloc	Quad Flat No-Lead	8V79S674NLGI	3D model available Symbol and footprint available 3	1 Download Model
	8533AGI-01LFT Renesas Electronics	1	The 8533I-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer. The 8533I-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8533I-01 ideal fo	Small Outline Packages	8533AGI-01LFT	3D model available Symbol and footprint available 3	1 Download Model
	74FCT3807ASOGI Renesas Electronics	1	The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS technology. This low skew clock driver offers 1:10 fanout. The large fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. The FCT3807/A offers low capacitance inputs with hysteresis for improved noise margins. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution.	Small Outline Packages	74FCT3807ASOGI	3D model available Symbol and footprint available 3	1 Download Model
	854S202AYILF Renesas Electronics	1	The 854S202I is a 12:2 Differential-to-LVDS Clock Multiplexer which can operate >3GHz. The 854S202I has 12 selectable differential clock inputs, any of which can be independently routed to either of the two LVDS outputs. The CLKx, nCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.	Quad Flat Packages	854S202AYILF	3D model available Symbol and footprint available 3	1 Download Model
	74FCT3807EPYGI8 Renesas Electronics	1	The FCT3807 is a 3.3V clock driver built using advanced CMOS technology. This low skew clock driver offers 1:10 fanout. The large fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution.	Small Outline Packages	74FCT3807EPYGI8	3D model available Symbol and footprint available 3	1 Download Model
	5V41067APGG Renesas Electronics	1	The 5V41067A is a 2:4 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The 5V41067A selects between 1 of 2 differential HCSL inputs to fanout to 4 differential HCSL output pairs. The outputs can also be terminated to LVDS.	Small Outline Packages	5V41067APGG	3D model available Symbol and footprint available 3	1 Download Model
	83052AGI-01LF Renesas Electronics	1	The 83052I-01 is a 2-bit, 2:1, Single-ended Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83052I-01 has two selectable single-ended clock inputs and two single-ended clock outputs. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. Possible applications include systems with up	Small Outline Packages	83052AGI-01LF	3D model available Symbol and footprint available 3	1 Download Model

	83052AGILF Renesas Electronics	1	The 83052I is a low skew, 2:1, Single-ended Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83052I has two selectable single-ended clock inputs and one single-ended clock output. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage trans-lation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. The device operates up to 250MHz and is packaged	Small Outline Packages	83052AGILF	3D model available Symbol and footprint available 3	1 Download Model
	8S58035AKILF Renesas Electronics	1	The 8S58035I is a high speed 2-to-6 Differential-to-LVPECL Fanout Buffer. The 8S58035I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel. The internally terminated differential inputs and VREF_AC pins allow other differential signal families such as LVDS, LVDS and CML to be easily interfaced to the input with minimal use of external components. The device also has a 2:1 MUX input, al	Quad Flat No-Lead	8S58035AKILF	3D model available Symbol and footprint available 3	1 Download Model
	9112AG-16LF Renesas Electronics	1	The IDT9112-16 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz.	Small Outline Packages	9112AG-16LF	3D model available Symbol and footprint available 3	1 Download Model
	9ZXL1231EKILF-1K/W Renesas Electronics	1	The 9ZXL1231E is a second-generation, enhanced performance DB1200ZL differential buffer. The part is a pin-compatible upgrade to the 9ZXL1231A, while offering much improved phase jitter performance and increased system security features. A fixed external feedback maintains low drift for critical QPI/UPI applications.	Quad Flat No-Lead	9ZXL1231EKILF-1K/W	3D model available Symbol and footprint available 3	1 Download Model
	8T33FS314PYGI Renesas Electronics	1	The IDT8T33FS314I is a low skew 1-to-4 Differential Fanout Buffer, designed with clock distribution in mind, accepting two clock sources into an input MUX. The MUX is controlled by a CLK_SEL pin. This makes the IDT8T33FS314I very versatile, in that, it can operate as both a differential clock buffer as well as a signal-level translator and fanout buffer. The device is designed on a SiGe process and can operate at frequencies in excess of 2.7GHz. This ensures negligible jitter introduction to the timing budg	Small Outline Packages	8T33FS314PYGI	3D model available Symbol and footprint available 3	1 Download Model
	853S012AKILFT Renesas Electronics	1	The 853S012I is an 12:1 Differential-to-3.3V or 2.5V LVPECL Clock/Data Multiplexer which can operate up to 3.2GHz. The 853S012I has twelve differential selectable clock inputs. The CLK, nCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors.	Quad Flat No-Lead	853S012AKILFT	3D model available Symbol and footprint available 3	1 Download Model
	8T79S828-08NLGI Renesas Electronics	1	The IDT8T79S828-08I is a high performance, 1-to-8, differential input to universal output clock divider and fanout buffer. The device is designed for frequency-division and signal fanout of high-frequency clock signals in applications requiring four different output frequencies generated simultaneously. Each bank of two outputs has a selectable divider value of ÷1 thru ÷6 and ÷8. TheIDT8T79S828-08I is optimized for 3.3V and 2.5V supply voltages and a temperature range of -40°C to 85°C. The device is package	Quad Flat No-Lead	8T79S828-08NLGI	3D model available Symbol and footprint available 3	1 Download Model
	MK2304S-1ILF Renesas Electronics	1	The MK2304-1 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter PLL techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The MK2304-1 includes two banks of two outputs each 1X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all 4 outputs. Compared to competitive CMOS devices, the MK2304-1 has the lowest jitter. IDT manufa	Small Outline Packages	MK2304S-1ILF	3D model available Symbol and footprint available 3	1 Download Model
	MK2304S-1ILFT Renesas Electronics	1	The MK2304-1 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter PLL techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The MK2304-1 includes two banks of two outputs each 1X. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all 4 outputs. Compared to competitive CMOS devices, the MK2304-1 has the lowest jitter. IDT manufa	Small Outline Packages	MK2304S-1ILFT	3D model available Symbol and footprint available 3	1 Download Model
	8SLVD2102NLGI8 Renesas Electronics	1	The 8SLVD2102I is a high-performance differential dual 1:2 LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD2102I is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2102I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two independent buffers with two low skew outputs each are availa	Quad Flat No-Lead	8SLVD2102NLGI8	3D model available Symbol and footprint available 3	1 Download Model
7 8 9 10 11 12 13 14 15

Can't find what you're looking for? Request this part

Clock Drivers Model Download Search Results

Popular Clock Drivers