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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72265LA10PFG Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V223L6BC Renesas Electronics	1	The 72V223 1K x 9/512 x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V223L6BC	3D model available Symbol and footprint available 3	1 Download Model
	72T1855L6-7BB Renesas Electronics	1	The 72T1855 is a 4K x 18 / 8K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1855L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	7205L20TDB Renesas Electronics	1	The 7205 is a 8K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7205L20TDB	3D model not available Symbol and footprint available 2	1 Download Model

	72V831L10PFG Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	7201LA50DB Renesas Electronics	1	The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7201LA50DB	3D model not available Symbol and footprint available 2	1 Download Model
	7204L12SOG8 Renesas Electronics	1	The 7204 is a 4K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7204L12SOG8	3D model available Symbol and footprint available 3	1 Download Model
	7204L12JG Renesas Electronics	1	The 7204 is a 4K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7204L12JG	3D model not available Symbol and footprint available 2	1 Download Model
	72225LB10TFG Renesas Electronics	1	The 72225 is a 1K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72225LB10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72615L35J Renesas Electronics	1	The 72615 is a 512 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Plastic Leaded Chip Carrier	72615L35J	3D model not available Symbol and footprint available 2	1 Download Model
	72V2103L15PFG Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V2103L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V225L10TFG Renesas Electronics	1	The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V225L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	7201LA50TDB Renesas Electronics	1	The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7201LA50TDB	3D model not available Symbol and footprint available 2	1 Download Model
	72V285L10PFG Renesas Electronics	1	The 72V285 is an 64K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72285 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V285L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72201L10JG Renesas Electronics	1	The 72201SyncFIFO™ is a 256 x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Plastic Leaded Chip Carrier	72201L10JG	3D model not available Symbol and footprint available 2	1 Download Model

	72230L10TPG Renesas Electronics	1	The 72230 is a 2K x 8 SyncFIFO™ with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs, such as graphics, Local Area Networks (LANs), and interprocessor communication. It has 8-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Dual-In-Line Packages	72230L10TPG	3D model available Symbol and footprint available 3	1 Download Model
	723624L15PFG8 Renesas Electronics	1	The 723624 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 256 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723624L15PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V283L7-5PFGI8 Renesas Electronics	1	The 72V283 64K x 9/32K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V283L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V3670L10PFG Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3670L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T18125L5BB Renesas Electronics	1	The 72T18125 is a 512K x 18 / 1M x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18125L5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V05L25JGI8 Renesas Electronics	1	The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V05L25JGI8	3D model available Symbol and footprint available 3	1 Download Model
	72285L10PFG Renesas Electronics	1	The 72285 is a 64K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72285L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T1875L6-7BB Renesas Electronics	1	The 72T1875 is a 16K x 18 / 32K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1875L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	7207L20JGI Renesas Electronics	1	The 7207 is a 32K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	7207L20JGI	3D model not available Symbol and footprint available 2	1 Download Model
	72V05L15JG8 Renesas Electronics	1	The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V05L15JG8	3D model available Symbol and footprint available 3	1 Download Model
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