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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	9DB106BFILF Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BFILF	3D model available Symbol and footprint available 3	1 Download Model
	9DB102BGILF Renesas Electronics	1	The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.	Small Outline Packages	9DB102BGILF	3D model available Symbol and footprint available 3	1 Download Model
	9DB102BGILFT Renesas Electronics	1	The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.	Small Outline Packages	9DB102BGILFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB102BFILFT Renesas Electronics	1	Renesas Electronics	Small Outline Packages	9DB102BFILFT	3D model available Symbol and footprint available 3	1 Download Model

	9DB106BFLF Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BFLF	3D model available Symbol and footprint available 3	1 Download Model
	9DB106BFLFT Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BFLFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB104BFLF Renesas Electronics	1	9DB104 is not recommended for new designs.	Small Outline Packages	9DB104BFLF	3D model available Symbol and footprint available 3	1 Download Model
	9DB104BFLFT Renesas Electronics	1	9DB104 is not recommended for new designs.	Small Outline Packages	9DB104BFLFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB102BFLFT Renesas Electronics	1	The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.	Small Outline Packages	9DB102BFLFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB102BGLF Renesas Electronics	1	The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.	Small Outline Packages	9DB102BGLF	3D model available Symbol and footprint available 3	1 Download Model
	9DB106BFILFT Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BFILFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB106BGLFT Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BGLFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB106BGLF Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BGLF	3D model available Symbol and footprint available 3	1 Download Model
	9DB106BGILF Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BGILF	3D model available Symbol and footprint available 3	1 Download Model
	9DB102BFLF Renesas Electronics	1	The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.	Small Outline Packages	9DB102BFLF	3D model available Symbol and footprint available 3	1 Download Model

	9DB102BGLFT Renesas Electronics	1	The 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.	Small Outline Packages	9DB102BGLFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB106BGILFT Renesas Electronics	1	The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.	Small Outline Packages	9DB106BGILFT	3D model available Symbol and footprint available 3	1 Download Model
	9DB104BGLF Renesas Electronics	1	9DB104 is not recommended for new designs.	Small Outline Packages	9DB104BGLF	3D model available Symbol and footprint available 3	1 Download Model
	9DB104BGLFT Renesas Electronics	1	9DB104 is not recommended for new designs.	Small Outline Packages	9DB104BGLFT	3D model available Symbol and footprint available 3	1 Download Model
	HP09DB105KN Yageo Group	1	HP LDD Indust X7R HT200C, Ceramic, 1 uF, 10%, 200 VDC, X7R, HighTemperature, 12.7 mm	Other	HP09DB105KN	3D model available Symbol and footprint available 3	1 Download Model
	9DB102BFILF Integrated Device Technology Inc	1	PLL Based Clock Driver, 9DB Series, 2 True Output(s), 0 Inverted Output(s), PDSO20		9DB102BFILF	3D model not available Symbol and footprint not available 0	0 Build or Request
	9DB108BGLF Renesas Electronics Corporation	1	PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48		9DB108BGLF	3D model not available Symbol and footprint not available 0	0 Build or Request
	9DB108BFLF Integrated Device Technology Inc	1	PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48		9DB108BFLF	3D model not available Symbol and footprint not available 0	0 Build or Request
	9DB106F-T Integrated Device Technology Inc	1	Clock Driver, PDSO28		9DB106F-T	3D model not available Symbol and footprint not available 0	0 Build or Request
	9DB106BGLF Integrated Device Technology Inc	1	PLL Based Clock Driver, 9DB Series, 6 True Output(s), 0 Inverted Output(s), PDSO28		9DB106BGLF	3D model not available Symbol and footprint not available 0	0 Build or Request
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