MC100 Footprint, Symbol and 3D Model search results

Showing 25 of 66518 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	MC100EPT25DR2G onsemi	1	Q Output will default LOW with inputs open or at GND; 24mA TTL outputs; Maximum Frequency > 275 MHz Typical; 1.1ns Typical Propagation Delay; Operating Range: VCC = 3.0 V to 3.6 V; VEE = -5.5 V to -3.0 V; GND = 0 V; VBB Output; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available	Small Outline Packages	MC100EPT25DR2G	3D model available Symbol and footprint available 3	1 Download Model
	MC100LVEP111MNG onsemi	1	MC100LVEP111MNG, ECL, HSTL, PECL Clock Driver ECL, PECL, 2-Input Maximum of 3 GHz, 32-Pin QFN	Quad Flat No-Lead	MC100LVEP111MNG	3D model available Symbol and footprint available 3	1 Download Model
	MC100LVEP05DTR2G onsemi	1	Low Output Jitter; 3 GHz Max Operating Freqency	Small Outline Packages	MC100LVEP05DTR2G	3D model available Symbol and footprint available 3	1 Download Model
	MC100EL32DG onsemi	1	5V ECL ÷2 Divider	Other	MC100EL32DG	3D model available Symbol and footprint available 3	1 Download Model

	MC100ELT24DG onsemi	1	TTL to ECL Translator, 1 Func, Complementary Output, ECL, PDSO8	Small Outline Packages	MC100ELT24DG	3D model available Symbol and footprint available 3	1 Download Model
	MC100ES6226AC Renesas Electronics	1	MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on backplanes of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. The MC100ES6226 can be operated from a 3.3 V or 2.5 V positive supply without the requirement of a negative supply line. E	Quad Flat Packages	MC100ES6226AC	3D model available Symbol and footprint available 3	1 Download Model
	MC100EPT23DTR2G onsemi	1	Q Output will default LOW with inputs open or at GND; 1.5ns Typical Propagation Delay; Maximum Operating Frequency > 275MHz; 24mA LVTTL Outputs; Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V; Open Input Default State; Pb-Free Packages are Available	Small Outline Packages	MC100EPT23DTR2G	3D model available Symbol and footprint available 3	1 Download Model
	MC100EP32DTG onsemi	1	PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V; 350ps Typical Propagation Delay; NECL Mode Operating Range: VCC= 0 V with VEE= –3.0 V to –5.5 V; Q Output will default LOW with inputs open or at VEE; Maximum Frequency > 4 GHz Typical; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available	Small Outline Packages	MC100EP32DTG	3D model available Symbol and footprint available 3	1 Download Model
	MC100EP40DTG onsemi	1	Maximum Frequency > 2 Ghz Typical; Fully Differential; Advanced High Band Output Swing of 400 mV; Theoretical Gain = 1.11; Trise 97 pS Typical, Ffall 70 pS Typical; The 100 Series Contains Temperature Compensation; PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; 50Ω Internal Termination Resistor; These are Pb-Free Devices	Small Outline Packages	MC100EP40DTG	3D model available Symbol and footprint available 3	1 Download Model
	MC100LVEL16DTG onsemi	1	300 ps Propagation Delay; ESD Protection: >2 KV HBM, > 200 V MM; The 100 Series Contains Temperature Compensation; High Bandwidth Output Transitions; PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V; NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V; Internal Input Pulldown Resistors on D, Pullup and Pulldown Resistors on Dbar; Q Output will Default LOW with Inputs Open or at VEE; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Inf	Small Outline Packages	MC100LVEL16DTG	3D model available Symbol and footprint available 3	1 Download Model
	MC100EP14DTG onsemi	1	100 ps Device-to-Device Skew; 25 ps Within Device Skew; 400 ps Typical Propagation Delay; Maximum Frequency > 2 GHz Typical; PECL and HSTL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V; Open Input Default State; The 100 Series Contains Temperature Compensation	Small Outline Packages	MC100EP14DTG	3D model available Symbol and footprint available 3	1 Download Model
	MC100EL11DG onsemi	1	NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V; PECL Mode Operating Range: VCC= 4.2 V to 5.7 with VEE= 0 V; ESD Protection: > 1 KV HBM, > 100 V MM; 5ps Skew Between Outputs; 265ps Propagation Delay; Internal Input Pulldown Resistors; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34; Transistor Count = 44 devices; Pb-Free Packages ar	Other	MC100EL11DG	3D model available Symbol and footprint available 3	1 Download Model
	MC100ES6130EJ Renesas Electronics	1	The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout buffer. The ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a 2:1 input MUX which is ideal for redundant clock switchover applications. This device also includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state to eliminate the possibility of a runt clock pulse.	Small Outline Packages	MC100ES6130EJ	3D model available Symbol and footprint available 3	1 Download Model
	MC100EP51DG onsemi	1	Maximum Frequency > 3 Ghz Typical; 350ps Typical Propagation Delay; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available	Small Outline Packages	MC100EP51DG	3D model available Symbol and footprint available 3	1 Download Model
	MC100EP131FAG onsemi	1	Q Output will default LOW with inputs open or at VEE; Individual Asynchronous Resets; PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; 460ps Typical Propagation Delay; Maximum Frequency > 3 GHz Typical; Differential Individual and Common Clocks; Asynchronous Set; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available	Quad Flat Packages	MC100EP131FAG	3D model available Symbol and footprint available 3	1 Download Model

	MC100EP52DG onsemi	1	330ps Typical Propagation Delay; Maximum Frequency > 4 GHz Typical; PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V; Q Output will default LOW with inputs open or at VEE; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available	Small Outline Packages	MC100EP52DG	3D model available Symbol and footprint available 3	1 Download Model
	MC100ES6221AE Renesas Electronics	1	The MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6221 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and t	Quad Flat Packages	MC100ES6221AE	3D model available Symbol and footprint available 3	1 Download Model
	MC100EL04DG onsemi	1	High Bandwidth Output Transitions; 240ps Propagation Delay; >1000V ESD Protection; 75kW Internal Input Pulldown Resistors; Pb-Free Packages are Available	Small Outline Packages	MC100EL04DG	3D model available Symbol and footprint available 3	1 Download Model
	MC100EL1648DG onsemi	1	ESD Protection: >2 KV HBM, >100 V MM; Typical Operating Frequency Up to 1100 MHz; Phase Noise -90 dBc/Hz at 25 kHz Typical; Low-Power 19 mA at 5.0 Vdc Power Supply; PECL Mode Operating Range: VCC= 5.0 V with VEE= 0 V; NECL Mode Operating Range: VCC= 0 V with VEE= -5.2 V; Input Capacitance= 6.0 pF (TYP); Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Maximum Series Resistance for L (External Inductance)= 50 W (TYP); Moisture Sensitivity Level 1. For Additional Information, see Application Note AND80	Small Outline Packages	MC100EL1648DG	3D model available Symbol and footprint available 3	1 Download Model
	MC100LVELT23DTG onsemi	1	2 Func, True Output, ECL, PDSO8	Small Outline Packages	MC100LVELT23DTG	3D model available Symbol and footprint available 3	1 Download Model
	MC100LVEL34DTG onsemi	1	Clock Generators & Support Products 3.3V ECL Clock Generator	Small Outline Packages	MC100LVEL34DTG	3D model available Symbol and footprint available 3	1 Download Model
	MC100LVEL30DWG onsemi	1	ON Semiconductor MC100LVEL30DWG Triple D Type Flip Flop IC, ECL, 3.3 → 3.8 V, 20-Pin SOIC	Small Outline Packages	MC100LVEL30DWG	3D model available Symbol and footprint available 3	1 Download Model
	MC100EL05DG onsemi	1	Logic Gates 5V ECL 2-Input Diff AND/NAND	Small Outline Packages	MC100EL05DG	3D model available Symbol and footprint available 3	1 Download Model
	MC100E116FNG onsemi	1	ON Semiconductor MC100E116FNG, Bus Buffer, 500ps, -4.2 → 5.7 V, 28-Pin PLCC	Plastic Leaded Chip Carrier	MC100E116FNG	3D model not available Symbol and footprint available 2	1 Download Model
	MC100EL30DW onsemi	1	Flip-Flops 5V ECL Triple D-Type	Small Outline Packages	MC100EL30DW	3D model available Symbol and footprint available 3	1 Download Model
1 2 3 4 5 6 7 8 9

Can't find what you're looking for? Request this part

MC100 Model Download Search Results

Popular Level Translators