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Image Part Number D.S Description Package Category Prices / Stock Model Action
Image Part Number D.S Description Package Category Prices / Stock Model Action
Part Image Part Image 1 220 ps Propagation Delay; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; Maximum Frequency > 4 GHz Typical (See Graph); PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; Open Input Default State; Safety Clamp on Inputs; Q Output Will Default LOW with Inputs Open or at VEE; VBB Output Small Outline Packages MC100EP16DG 1 Download Model
Part Image Part Image 1 MC100LVEP111MNG, ECL, HSTL, PECL Clock Driver ECL, PECL, 2-Input Maximum of 3 GHz, 32-Pin QFN Quad Flat No-Lead MC100LVEP111MNG 1 Download Model
Part Image Part Image 1 Maximum Frequency > 4 GHz Typical; 240 ps Propagation Delay; NECL Mode Operating Range: VCC=0 V with VEE= -2.375 V to -3.8 V; VBB Output; PECL Mode Operating Range: VCC= 2.375 V to 3.8 V with VEE=0 V; Open Input Default State; LVDS Input Compatible Small Outline Packages MC100LVEP16DTG 1 Download Model
Part Image Part Image 1 Q Output will default LOW with inputs open or at GND; 1.5ns Typical Propagation Delay; Maximum Operating Frequency > 275MHz; 24mA LVTTL Outputs; Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V; Open Input Default State; Pb-Free Packages are Available Small Outline Packages MC100EPT23DR2G 1 Download Model
Part Image Part Image 1 330ps Typical Propagation Delay; Maximum Frequency > 4 GHz Typical; PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V; Q Output will default LOW with inputs open or at VEE; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available Small Outline Packages MC100EP52DR2G 1 Download Model
Part Image Part Image 1 Maximum Input Clock Frequency >1.2 GHz Typical; Programmable Range: 0 ns to 10 ns; Delay Range: 2.2 ns to 12.4 ns; 10 ps Increments; Linearity 40 ps max; PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V; NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V; IN/INb Inputs Accept LVPECL, LVNECL, LVDS Levels; A Logic High on the ENb Pin Will Force Q to Logic Low; D10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels; VBB Output Reference Voltage Quad Flat No-Lead MC100EP196BMNG 1 Download Model
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MC100ES6130EJR2 Renesas Electronics
1 The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout buffer. The ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a 2:1 input MUX which is ideal for redundant clock switchover applications. This device also includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state to eliminate the possibility of a runt clock pulse. Small Outline Packages MC100ES6130EJR2 1 Download Model
Part Image Part Image 1 Maximum Frequency > 3 Ghz Typical; NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V; 250 ps Typical Propagation Delay; PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V; Open Input Default State; Safety Clamp on Inputs; Q Output Will Default LOW with Inputs Open or at VEE Small Outline Packages MC100EP08DTG 1 Download Model
Part Image Part Image 1 PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V; 350ps Typical Propagation Delay; NECL Mode Operating Range: VCC= 0 V with VEE= –3.0 V to –5.5 V; Q Output will default LOW with inputs open or at VEE; Maximum Frequency > 4 GHz Typical; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available Small Outline Packages MC100EP32DG 1 Download Model
Part Image Part Image 1 <100ps Output-to-Output Skew; Flow Through Pinouts; ESD Protection: >4 KV HBM, >200 V MM; The 100 Series Contains Temperature Compensation; 350ps Typical Propagation Delay; LVPECL Operating Range: VCC= 3.15 V to 3.45 V with GND= 0 V; When Unused TTL Input is left Open, Q Output will Default High; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34; Tr Small Outline Packages MC100LVELT22DR2G 1 Download Model
Part Image Part Image 1 Maximum Input Clock Frequency >1.2 GHz Typical; Programmable Range: 0 ns to 10 ns; Delay Range: 2.2 ns to 12.2 ns; 10 ps Increments; PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V; NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V; IN/INb Inputs Accept LVPECL, LVNECL, LVDS Levels; A Logic High on the EN Pin Will Force Q to Logic Low; D10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels; VBB Output Reference Voltage Quad Flat Packages MC100EP195BFAG 1 Download Model
Part Image Part Image 1 Flip Flop 2 Element D-Type 1 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width) Small Outline Packages MC100LVEL29DWR2G 1 Download Model
Part Image Part Image 1 > 3 GHz Minimum Shift Frequency; 9-Bit for Byte-Parity Applications; Asynchronous Master Reset; Dual Clocks; PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V; Open Input Default State; Safety Clamp on Inputs Other MC100EP142FAG 1 Download Model
Part Image Part Image 1 50 ps Typical Output-to-Output Skew; Synchronous Enable/Disable; Master Reset for Synchronization; 1.5 GHz Toggle Frequency; The 100 Series Contains Temperature Compensation.; PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0V; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V; Open Input Default State; LVDS Input Compatible; Pb-Free Packages are Available Small Outline Packages MC100LVEL34DTR2G 1 Download Model
Part Image Part Image 1 Flip Flop 1 Element D-Type 1 Bit Positive, Negative 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Small Outline Packages MC100LVEL51DTR2G 1 Download Model
Part Image Part Image 1 35 ps Output-to-Output Skew; Synchronous Enable/Disable; Master Reset for Synchronization; The 100 Series Contains Temperature Compensation.; PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V; Open Input Default State; LVDS Input Compatible Small Outline Packages MC100LVEP34DG 1 Download Model
Part Image Part Image 1 Maximum Frequency > 3 Ghz Typical; NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V; PECL Mode Operating Range:VCC= 3.0 V to 5.5 V with VEE= 0 V; 220ps Typical Propagation Delay; Open Input Default State; Safety Clamp on Inputs; Q Output Will Default LOW with Inputs Open or at VEE; Pb-Free Packages are Available Small Outline Packages MC100EP05DTR2G 1 Download Model
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MC100ES6014EJ Renesas Electronics
1 The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions. The ES6014 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure that Small Outline Packages MC100ES6014EJ 1 Download Model
Part Image Part Image 1 2.0ns Typical Propagation Delay; PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with GND= 0 V; Maximum Frequency > 180 MHz; Flow Through Pinouts; Internal Pulldown Resistors; Differential LVPECL Inputs; 24 mA LVTTL Outputs; Q Output will default LOW with inputs open or at GND; ESD Protection: >1.5 KV HBM, >100 V MM; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; Flammability Rating: UL-94 code V-0 @ 1/8", Oxyge Small Outline Packages MC100LVELT23DTRG 1 Download Model
Part Image Part Image 1 2 Func, True Output, ECL, PDSO8 Small Outline Packages MC100LVELT23DTG 1 Download Model
Part Image Part Image 1 ECL to PECL Translator, 3 Func, Complementary Output, ECL, PDSO20 Small Outline Packages MC100LVEL90DWG 1 Download Model
Part Image Part Image 1 ON Semiconductor MC100E116FNG, Bus Buffer, 500ps, -4.2 → 5.7 V, 28-Pin PLCC Plastic Leaded Chip Carrier MC100E116FNG 1 Download Model
Part Image Part Image 1 Logic Gates 5V ECL 2-Input Diff AND/NAND Small Outline Packages MC100EL05DG 1 Download Model
Part Image Part Image 1 ON Semiconductor MC100LVEL30DWG Triple D Type Flip Flop IC, ECL, 3.3 → 3.8 V, 20-Pin SOIC Small Outline Packages MC100LVEL30DWG 1 Download Model
Part Image Part Image 1 Flip-Flops 5V ECL Triple D-Type Small Outline Packages MC100EL30DW 1 Download Model
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