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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	9ZXL0651AKLF Renesas Electronics	1	The 9ZXL0651 is a low-power 6-output differential buffer that meets all the performance requirements of the Intel DB1200Z specification. It consumes 50% less power than standard HCSL devices and has internal terminations to allow direct connection to 85 ohm transmission lines. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.	Quad Flat No-Lead	9ZXL0651AKLF	3D model available Symbol and footprint available 3	1 Download Model
	NB6L14SMNG onsemi	1	Maximum Input Clock Frequency > 2.0 GHz; Maximum Input Data Rate > 2.5 Gbps; 1ps Maximum of RMS Clock Jitter; 120ps Typical Rise and Fall Times; VREFAC Reference Output	Quad Flat No-Lead	NB6L14SMNG	3D model available Symbol and footprint available 3	1 Download Model
	551SDCGI8 Renesas Electronics	1	The 551S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 551S has best in class Additive Phase Jitter of sub 50 fsec.	Small Outline Packages	551SDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	663MILF Renesas Electronics	1	The IDT663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the IDT674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies. The phase detector and VCO functions of the device can also be used independently. This enables the config	Small Outline Packages	663MILF	3D model available Symbol and footprint available 3	1 Download Model

	9DMV0141BKILF Renesas Electronics	1	The 9DMV0141 is a member of Renesas' SOC-Friendly 1.8 V Very-Low-Power (VLP) PCIe Gen1–5 family. The 9DMV0141 has integrated output terminations for direct connection to 100Ω transmission lines. The output has an OE# pin for optimal system control and power management. The parts provide asynchronous or glitch-free switching modes.	Quad Flat No-Lead	9DMV0141BKILF	3D model available Symbol and footprint available 3	1 Download Model
	670M-01ILF Renesas Electronics	1	The 670-01 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of IDT's ClockBlocks™ family, the part's zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs giving the appearance of no delay through the device. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin. The 670-01	Small Outline Packages	670M-01ILF	3D model available Symbol and footprint available 3	1 Download Model
	83905AKLF Renesas Electronics	1	The 83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. The 83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply mode. Guaranteed output and part-to-part skew characteristics along with the 1.8V ou	Quad Flat No-Lead	83905AKLF	3D model available Symbol and footprint available 3	1 Download Model
	8535AGI-01LF Renesas Electronics	1	The 8535I-01 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The 8535I-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8535I-01 ideal for those applications d	Small Outline Packages	8535AGI-01LF	3D model available Symbol and footprint available 3	1 Download Model
	2510CGT-CQ0 Renesas Electronics	1	The 2510C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The 2510C operates at 3.3V VCC and drives up to ten clock loads.	Small Outline Packages	2510CGT-CQ0	3D model available Symbol and footprint available 3	1 Download Model
	9P960AFLF Renesas Electronics	1	Dual Channel DDRII/III Zero Delay Buffer	Small Outline Packages	9P960AFLF	3D model available Symbol and footprint available 3	1 Download Model
	MPC962305EF-1H Renesas Electronics	1	The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0	Small Outline Packages	MPC962305EF-1H	3D model available Symbol and footprint available 3	1 Download Model
	2309NZ-1HDCG8 Renesas Electronics	1	The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback to a PLL. The IDT2309NZ operates at 3.3V and outputs can run up to 133.33MHz The IDT2309NZ is designed for low EMI and power optimization. It has multiple VDD and VSS pins for noise optimization and consumes less than 32mA at 66	Small Outline Packages	2309NZ-1HDCG8	3D model available Symbol and footprint available 3	1 Download Model
	9DBV0531AKILFT Renesas Electronics	1	The 9DBV0531is a member of IDT's Full-Featured PCIe family. The device has 5 output enables for clock management, and 3 selectable SMBus addresses.	Quad Flat No-Lead	9DBV0531AKILFT	3D model available Symbol and footprint available 3	1 Download Model
	580G-01LF Renesas Electronics	1	The 580-01 is a clock multiplexer (mux) designed to switch between two clock sources with no glitches or short pulses. The operation of the mux is controlled by an input pin but the part can also be configured to switch automatically if one of the input clocks stops. The part also provides clock detection by reporting when an input clock has stopped. For a clock mux with zero delay and smooth switching, see either the 581-01 or the 581-02.	Small Outline Packages	580G-01LF	3D model available Symbol and footprint available 3	1 Download Model
	RC19016A100GN1#KB0 Renesas Electronics	1	The RC19016 is a 16-output PCIe Gen6 buffer that is backward compatible to earlier PCIe generations. The RC19016 provides ultra-low additive jitter and reduced in-to-out delay performance for better design-margin and incorporates several features for easier and more robust design.	Quad Flat No-Lead	RC19016A100GN1#KB0	3D model available Symbol and footprint available 3	1 Download Model

	850S1201BGILFT Renesas Electronics	1	The 850S1201I is a low skew12:1 Single-ended Clock Multiplexer. The 850S1201I has 12 selectable single-ended clock inputs and 1 single-ended clock output. The device operates up to 250MHz and is packaged in a 20 TSSOP package.	Small Outline Packages	850S1201BGILFT	3D model available Symbol and footprint available 3	1 Download Model
	9DBL0651CKILFT Renesas Electronics	1	The 9DBL0651 6-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0651 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.For information regarding evaluation boards and material, please contact your local sales representative.	Quad Flat No-Lead	9DBL0651CKILFT	3D model available Symbol and footprint available 3	1 Download Model
	9DMU0141AKILF Renesas Electronics	1	The 9DMU0141 is a member of IDT's SOC-Friendly 1.5 V Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has integrated output terminations providing Zo=100 ohms for direct connection to 100 ohm transmission lines. The output has an OE# pin for optimal system control and power management. The part provides asynchronous or glitch-free switching modes.	Quad Flat No-Lead	9DMU0141AKILF	3D model available Symbol and footprint available 3	1 Download Model
	49FCT20805PYGI Renesas Electronics	1	The FCT20805 is a 2.5 volt clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT20805 offers low capacitance inputs. The FCT20805 is designed for high speed clock distribution where signal quality and skew are critical. The	Small Outline Packages	49FCT20805PYGI	3D model available Symbol and footprint available 3	1 Download Model
	2309NZ-1HDCGI Renesas Electronics	1	The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback to a PLL. The IDT2309NZ operates at 3.3V and outputs can run up to 133.33MHz The IDT2309NZ is designed for low EMI and power optimization. It has multiple VDD and VSS pins for noise optimization and consumes less than 32mA at 66	Small Outline Packages	2309NZ-1HDCGI	3D model available Symbol and footprint available 3	1 Download Model
	8P34S1212NLGI Renesas Electronics	1	The 8P34S1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals. The 8P34S1212 supports fail-safe operation and is characterized to operate from a 1.8V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable diffe	Quad Flat No-Lead	8P34S1212NLGI	3D model available Symbol and footprint available 3	1 Download Model
	23S08-1HDCGI8 Renesas Electronics	1	SOIC 150 MIL	Small Outline Packages	23S08-1HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	PI6C20400ALEX Diodes Incorporated	1	Clock Buffer 1:4 PCI Express Gen 2 Zero Delay Buffer	Small Outline Packages	PI6C20400ALEX	3D model available Symbol and footprint available 3	1 Download Model
	49FCT3805BPYGI Renesas Electronics	1	The FCT3805B is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The FCT3805B offers low capacitance inputs with hysteresis. The FCT3805B is designed for high speed clock distribution where	Small Outline Packages	49FCT3805BPYGI	3D model available Symbol and footprint available 3	1 Download Model
	5T30553DCG Renesas Electronics	1	The IDT5T30553 is a low skew, single input to four output, clock buffer. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs.	Small Outline Packages	5T30553DCG	3D model available Symbol and footprint available 3	1 Download Model
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