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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	NB3V8312CFAG onsemi	1	VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V; VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO; 250 MHz Maximum Clock Frequency; Accepts LVCMOS, LVTTL Clock Inputs; 12 LVCMOS Clock Outputs; 150 ps Max. Skew Between Outputs; Temp. Range 40C to +85C; 32pin LQFP and QFN Packages; Synchronous Clock Enable	Quad Flat Packages	NB3V8312CFAG	3D model available Symbol and footprint available 3	1 Download Model
	23S08E-4DCGI Renesas Electronics	1	3.3V Zero Delay Clock Multiplier, Spread Spectrum Compatible	Small Outline Packages	23S08E-4DCGI	3D model available Symbol and footprint available 3	1 Download Model
	23S08-1HDCGI8 Renesas Electronics	1	SOIC 150 MIL	Small Outline Packages	23S08-1HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	671M-01LF Renesas Electronics	1	Zero Delay, Low Skew Buffer and Multiplier	Small Outline Packages	671M-01LF	3D model available Symbol and footprint available 3	1 Download Model

	2305B-1HDCG8 Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1HDCG8	3D model available Symbol and footprint available 3	1 Download Model
	8T49N488A-999ASGI Renesas Electronics	1	The IDT8T49N488I is a quad PLL with FemtoClock® NG technology, integrating low phase noise Frequency Translator / Synthesizer, Jitter attenuator, and alarm and monitoring functions suitable for networking and communications applications. The device has four fully independent PLLs, each PLL is able to generate any output frequency in the 0.98MHz - 312.5MHz range and most output frequencies in the 312.5MHz - 1,300MHz range. A wide range of input reference clocks and operation reference clock may be used as th	BGA	8T49N488A-999ASGI	3D model available Symbol and footprint available 3	1 Download Model
	8316AKLF Renesas Electronics	1	The 8316 is a low skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer with 1.2V LVCMOS Outputs and a member of the family of High Performance Clock Solutions from IDT. The 8316 single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. Guaranteed output and part-to-part skew characteristics along with the 1.2V output makes the 8316 ideal for high performance, single ended applications that also require a li	Quad Flat No-Lead	8316AKLF	3D model available Symbol and footprint available 3	1 Download Model
	8530DYLF/W Renesas Electronics	1	The 8530 is a low skew, 1-to-16 Differential-to- 2.5V LVPECL Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV, as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the 8530 ideal for those clock distribution applications demanding well defined performance and repeatability.	Quad Flat Packages	8530DYLF/W	3D model available Symbol and footprint available 3	1 Download Model
	621MLFT Renesas Electronics	1	The 621 is a low skew, single input to four output, clock buffer. The device operates from a single 1.2 to 1.8 volt supply and has a 3.3 volt tolerant input, making it ideal for level translation. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs.	Small Outline Packages	621MLFT	3D model available Symbol and footprint available 3	1 Download Model
	QS5917T-132TQG Renesas Electronics	1	The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. In addition, TTL level outputs reduce clock signal noise. Various combinations of feedback and a divide-by-2 i	Small Outline Packages	QS5917T-132TQG	3D model available Symbol and footprint available 3	1 Download Model
	2308A-4DCG8 Renesas Electronics	1	The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the	Small Outline Packages	2308A-4DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2308-1HDCGI8 Renesas Electronics	1	The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the i	Small Outline Packages	2308-1HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	8737AGI-11LF Renesas Electronics	1	The 8737I-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737I-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8737I-11 ideal	Small Outline Packages	8737AGI-11LF	3D model available Symbol and footprint available 3	1 Download Model
	9DBU0741AKILF Renesas Electronics	1	The 9DBU0741 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 ohm transmission lines. The device has 7 output enables for clock management, and 3 selectable SMBus addresses.	Quad Flat No-Lead	9DBU0741AKILF	3D model available Symbol and footprint available 3	1 Download Model
	8343AY-01LF Renesas Electronics	1	The 8343-01 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The 8343-01 single ended clock input accepts LVCMOS or LVTTL input levels. The 8343-01 operates at 3.3V, 2.5V and mixed 3.3V input and 2.5V supply modes over the commercial temperature range. Guaranteed output and part-to-part skew characteristics make the 8343-01 ideal for those clock distribution applications demanding well defined performance and repeatability.	Quad Flat Packages	8343AY-01LF	3D model not available Symbol and footprint available 2	1 Download Model

	MPC942CAC Renesas Electronics	1	The MPC942 is a 1:18 low voltage clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device is offered in two versions; the MPC942C has an LVCMOS input clock while the MPC942P has a LVPECL input clock. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50? series or parallel terminated transmission lines. With output-to-output skews of 200ps, the MPC942 is ideal as a clock distribution chip for the most demanding of synchronous systems. The 2.5V o	Quad Flat Packages	MPC942CAC	3D model not available Symbol and footprint available 2	1 Download Model
	RC19013AGNG#KB0 Renesas Electronics	1	The RC19013 is a 13-output PCIe Gen6 buffer that is backward compatible to earlier PCIe generations. The RC19013 provides ultra-low additive jitter and reduced in-to-out delay performance for better design-margin and incorporates several features for easier and more robust design.	Quad Flat No-Lead	RC19013AGNG#KB0	3D model available Symbol and footprint available 3	1 Download Model
	83052AGI-01LFT Renesas Electronics	1	The 83052I-01 is a 2-bit, 2:1, Single-ended Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83052I-01 has two selectable single-ended clock inputs and two single-ended clock outputs. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. Possible applications include systems with up	Small Outline Packages	83052AGI-01LFT	3D model available Symbol and footprint available 3	1 Download Model
	CDC351IDBR Texas Instruments	1	IC CLK BUFFER 1:10 100MHZ 24SSOP	Small Outline Packages	CDC351IDBR	3D model available Symbol and footprint available 3	1 Download Model
	98ULPA877AKLF Renesas Electronics	1	1.8V Low power 1 to 10 differential clock distribution. Operating frequency: 125MHz to 410MHz	Quad Flat No-Lead	98ULPA877AKLF	3D model available Symbol and footprint available 3	1 Download Model
	87002AG-02LFT Renesas Electronics	1	The 87002-02 is a highly versatile 1:2 Differential-to- LVCMOS/LVTTL Clock Generator. The 87002-02 has a differential clock input. The CLK, nCLK pair can accept most standard differential input levels. Internal bias on the nCLK input allows the CLK input to accept LVCMOS/LVTTL. The 87002-02 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider	Small Outline Packages	87002AG-02LFT	3D model available Symbol and footprint available 3	1 Download Model
	74FCT3807SQGI8 Renesas Electronics	1	The 74FCT3807S is a low skew, single input to ten output, LVCMOS clock buffer. The 74FCT3807S has best in class additive phase Jitter of sub 50 fsec.	Small Outline Packages	74FCT3807SQGI8	3D model available Symbol and footprint available 3	1 Download Model
	74FCT3807SPGGI8 Renesas Electronics	1	The 74FCT3807S is a low skew, single input to ten output, LVCMOS clock buffer. The 74FCT3807S has best in class additive phase Jitter of sub 50 fsec.	Small Outline Packages	74FCT3807SPGGI8	3D model available Symbol and footprint available 3	1 Download Model
	8T49N4811NLGI8 Renesas Electronics	1	The 8T49N4811 is a highly flexible FemtoClock® NG pin-programmable clock generator suitable for networking and communications applications. It is able to generate five different output frequencies with multiple copies of each. A fundamental mode crystal, single-ended, or differential input reference may be used as the source for the output frequency. The use of pin-programming to select the input source / frequency, desired output frequencies and output styles allow a single device to be used in a wide vari	Quad Flat No-Lead	8T49N4811NLGI8	3D model available Symbol and footprint available 3	1 Download Model
	5V2305NRGI8 Renesas Electronics	1	The IDT5V2305 is a high performance, low skew clock buffer that operates up to 200MHz. One bank of five outputs provides low skew copies of CLK. Through the use of control pin G, the outputs of bank Y(0:4) can be placed in a low state regardless of CLK input. The device operates in 2.5V and 3.3V environments. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. The IDT5V2305 is characterized for operation from -40°C to +85°C.	Other	5V2305NRGI8	3D model available Symbol and footprint available 3	1 Download Model
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