Showing 25 of 10385 results
| Image | Part Number | D.S | Description | Package Category | Prices / Stock | Model | Action |
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| Image | Part Number | D.S | Description | Package Category | Prices / Stock | Model | Action |
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W25N512GVPIT
Winbond
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1 | 512Mb Serial NAND Flash Memory with uniform 2KB+64B page size and set Buffer Read Mode as default | Small Outline No-lead | W25N512GVPIT |
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W972GG6KB-3
Winbond
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1 | WFBGA84 | BGA | W972GG6KB-3 |
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W29N02KVSIAE
Winbond
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1 | Basic Features– Density: 2Gbit (Single chip solution)– Vcc: 2.7V to 3.6V– Bus width: x8– Operating temperature Industrial: -40°C to 85°C Industrial Plus: -40°C to 105°C Single-Level Cell (SLC) technology. Organization– Density: 2G-bit/256M-byte– Page size 2,176 bytes– Block size 64 pages Highest Performance– Read performance (Max.) Random read: 25us Sequential read cycle: 25ns– Write Erase performance Page program time: 250us (typ.) Block erase time: 2ms | Small Outline Packages | W29N02KVSIAE |
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W63AH6NBVABE
Winbond
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1 | This is a 1Gb Low Power DDR3 SDRAM organized as 8M words x 8 banks x 16bits | BGA | W63AH6NBVABE |
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W25N01JWTBIT
Winbond
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1 | New W25N Family of SpiFlash Memories– W25N01JW: 1G-bit / 128M-Byte– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold,– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3– Compatible SPI Serial Flash commands Highest Performance Serial NAND Flash– 166MHz Standard/Dual/Quad SPI clocks– 332/664MHz equivalent Dual/Quad SPI– DTR (Dual Transfer Rate) up to 80MHz– 80MB/s continuous data transfer rate– Fast Program/Erase performance– More than 100,000 erase/program | BGA | W25N01JWTBIT |
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W25Q64JWZEIQ
Winbond
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1 | 64Mb Serial NOR Flash 133MHz SON8 | Small Outline No-lead | W25Q64JWZEIQ |
3
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W9751G8NB-3K
Winbond
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1 | Power Supply: VDD, VDDQ = 1.8 V ± 0.1V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS andDQS) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK andCLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data | BGA | W9751G8NB-3K |
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W632GU8RB09A
Winbond
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1 | 2Gb DDR3 SDRAM 2133MHz VFBGA96 | BGA | W632GU8RB09A |
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W25Q01NWZEJM
Winbond
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1 | New Family of SpiFlash Memories– W25Q01NW: two 512M-bit / 128M-byte– Standard SPI: CLK, /CS, DI, DO– Dual SPI: CLK, /CS, IO0, IO1,– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3– 3 or 4-Byte Addressing Mode– Software & Hardware Reset(1) Highest Performance Serial Flash– 133MHz Standard/Dual/Quad SPI clocks– 266/532MHz equivalent Dual/Quad SPI– 66MB/S continuous data transfer rate– Min. 100K Program-Erase cycles– More than 20-year data retention Efficient “Continuous Read”– Quad Peri | Small Outline No-lead | W25Q01NWZEJM |
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W634GU8RB12J
Winbond
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1 | DDR3 SDRAM 1600MHz | BGA | W634GU8RB12J |
3
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W29N08GVSAAF
Winbond
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1 | 8Gb SLC NAND Flash MHz TSOPI48 | Small Outline Packages | W29N08GVSAAF |
3
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W25N512GVEAG
Winbond
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1 | 512Mb QspiNAND Flash 166MHz SON8 | Small Outline No-lead | W25N512GVEAG |
3
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W634GU8NB15W
Winbond
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1 | DDR3 SDRAM 1333MHz | BGA | W634GU8NB15W |
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W632GU6NB15W
Winbond
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1 | 2Gb DDR3 SDRAM 1333MHz VFBGA96 | BGA | W632GU6NB15W |
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W66AQ6NBHAHA
Winbond
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1 | BGA100 | BGA | W66AQ6NBHAHA |
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W29N01HVBINA
Winbond
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1 | 1Gb SLC NAND Flash MHz VFBGA63 | BGA | W29N01HVBINA |
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W25Q80DVSNIG
Winbond
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1 | Family of SpiFlash Memories– W25Q80DV: 8M-bit/1M-byte (1,048,576)– 256-byte per programmable page– Standard SPI: CLK,/CS,DI,DO,/WP,/Hold– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3– Uniform 4KB Sectors, 32KB & 64KB Blocks• Highest Performance Serial Flash– 104MHz Dual/Quad SPI clocks– 208/416MHz equivalent Dual/Quad SPI– 50MB/S continuous data transfer rate• Software and Hardware Write Protection– Write-Protect all or portion of memory– Enable/ | Small Outline Packages | W25Q80DVSNIG |
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W25Q64JVZESQ
Winbond
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1 | New Family of SpiFlash Memories– W25Q64JV: 64M-bit / 8M-byte– Standard SPI: CLK, /CS, DI, DO– Dual SPI: CLK, /CS, IO0, IO1– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3– Software & Hardware Reset(1) Highest Performance Serial Flash– 133MHz Single, Dual/Quad SPI clocks– 266/532MHz equivalent Dual/Quad SPI– Min. 100K Program-Erase cycles per sector– More than 20-year data retention Low Power, Wide Temperature Range– Single 2.7 to 3.6V supply– <1µA Power-down (typ.)– -40°C to +85°C op | Small Outline No-lead | W25Q64JVZESQ |
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W634GG8NB11J
Winbond
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1 | DDR3 SDRAM 1866MHz | BGA | W634GG8NB11J |
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W968D6DAGX7I
Winbond
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1 | This is a 256M bit CellularRAM™ compliant products, organized as 16M word by 16 bite; high-speed, CMOS pseudo-static random access memories developed for low-power, portable applications. | BGA | W968D6DAGX7I |
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W948V6KBHX6E
Winbond
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1 | 256Mb Low Power DDR SDRAM 333MHz VFBGA60 | BGA | W948V6KBHX6E |
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W634GG8NB11I
Winbond
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1 | 4Gb DDR3 SDRAM 1866MHz VFBGA78 | BGA | W634GG8NB11I |
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W631GG6MB09W
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w | BGA | W631GG6MB09W |
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W632GG6MB11K
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w | BGA | W632GG6MB11K |
3
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W631GG8MB09W
Winbond
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1 | Power Supply: VDD, VDDQ = 1.5V ± 0.075V Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation 8 bit prefetch architecture CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) Programmable read burst ordering: interleaved or nibble sequential Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w | BGA | W631GG8MB09W |
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