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Image Part Number D.S Description Package Category Prices / Stock Model Action
Image Part Number D.S Description Package Category Prices / Stock Model Action
Part Image Part Image 1 2 Func, True Output, ECL, PDSO8 Small Outline Packages MC100LVELT23DTG 1 Download Model
Part Image Part Image 1 D Flip-Flop, 100E Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, ECL, PDSO8 Small Outline Packages MC100EP31DG 1 Download Model
Part Image Part Image 1 D Flip-Flop, 100EL Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, ECL, PDSO8 Small Outline Packages MC100EL31DTG 1 Download Model
Part Image Part Image 1 MC100EP809FAG, Clock Generator HSTL, LVDS, PECL HSTL 2-Input, 32-Pin LQFP Quad Flat Packages MC100EP809FAG 1 Download Model
Part Image Part Image 1 Active Delay Line, Programmable, 1-Func, 1023-Tap, Complementary Output, ECL, PQFP32 Quad Flat Packages MC100EP195FA 1 Download Model
Part Image Part Image 1 Flip Flops 5V ECL JK Type Small Outline Packages MC100EL35DG 1 Download Model
Part Image Part Image 1 2 Input XOR/XNOR Configurable 1 Circuit 2 Input 8-SOIC Small Outline Packages MC100EL07DR2 1 Download Model
Part Image Part Image 1 Q Output will default LOW with inputs open or at GND; 24mA TTL outputs; Maximum Frequency > 275 MHz Typical; 1.1ns Typical Propagation Delay; Operating Range: VCC = 3.0 V to 3.6 V; VEE = -5.5 V to -3.0 V; GND = 0 V; VBB Output; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available Small Outline Packages MC100EPT25DTG 1 Download Model
Part Image Part Image 1 Maximum Frequency > 3 GHz Typical; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0V to -5.5V; Q Output will default LOW with inputs open or at VEE; 410 ps Propagation Delay; PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; Open Input Default State; Pb-Free Packages are Available Small Outline Packages MC100EP35DTG 1 Download Model
Part Image Part Image 1 3.2 Gb/s Typical Data Rate Capability; Differential Clock and Serial Inputs; VBB Output for Single-ended Input Applications; Asynchronous Data Reset (SYNC); PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; Open Input Default State; Safety Clamp on Inputs; Parallel Interface Can Support PECL, TTL and CMOS; Pb-Free Packages are Available Other MC100EP446FAG 1 Download Model
Part Image Part Image 1 ESD Protection: > 1 KV HBM, > 100 V MM; NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V; PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V; 260ps Propagation Delay; Internal Input Pulldown Resistors; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34; Transistor Count = 47 devices; Pb-Free Packages are Available Small Outline Packages MC100EL07DR2G 1 Download Model
Part Image Part Image 1 450 ps Typical Propagation Delay; Maximum Frequency > 3.0 GHz Typical; 20 ps Skew Within Device, 35 ps Skew Device-To-Device; PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V; Asynchronous Master Reset; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available Other MC100EP451FAG 1 Download Model
Part Image Part Image 1 Q Output will default LOW with inputs open or at GND; 1.5ns Typical Propagation Delay; Maximum Operating Frequency > 275MHz; 24mA LVTTL Outputs; Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V; Open Input Default State; Pb-Free Packages are Available Small Outline Packages MC100EPT23DG 1 Download Model
Part Image Part Image 1 PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V; Useful as Either 4:1 or 2:1 Multiplexer; VBB Output for Single-Ended Operation; NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V; Internal Input Pulldown Resistors on D(s) and SEL(s).; Pb-Free Packages are Available Other MC100EL57DG 1 Download Model
Part Image Part Image 1 Maximum Frequency > 3 Ghz Typical; NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V; PECL Mode Operating Range:VCC= 3.0 V to 5.5 V with VEE= 0 V; 220ps Typical Propagation Delay; Open Input Default State; Safety Clamp on Inputs; Q Output Will Default LOW with Inputs Open or at VEE; Pb-Free Packages are Available Small Outline Packages MC100EP05DTG 1 Download Model
Part Image Part Image 1 Maximum Frequency >3 Ghz; NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V; 85 ps Typical Device-to-Device Skew; VBBOutput; PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V; 350 ps Typical Propagation Delay; 20 ps Typical Output-to-Output Skew; Jitter Less than 1 ps RMS; The 100 Series Contains Temperature Compensation; Open Input Default State; LVDS Input Compatible Quad Flat Packages MC100LVEP210FARG 1 Download Model
Part Image Part Image 1 260 ps Typical Propagation Delay; Voltage Supplies VCC = 3.0 V to 5.5 V, VEE = -3.0 V to -5.5 V, GND = 0 V; Fully Differential Design; Q Output will default LOW with inputs open or at VEE; Maximum Frequency > 3 GHz Typical; VBB Output; Open Input Default State; Safety Clamp on Inputs; These are Pb-Free Devices Small Outline Packages MC100EP90DTG 1 Download Model
Part Image Part Image 1 Maximum Frequency > 1.2 Ghz Typical; PECL Mode Operating Range: VCC = 3.0 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V; A Logic High on the ENbar Pin Will Force Q to Logic Low; VBB Output Reference Voltage; D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs.; Programmable Range: 2.2 ns to 12.2 ns; 10 ps Increments; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available Quad Flat Packages MC100EP195FAG 1 Download Model
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MC100ES6011EFR2 Renesas Electronics
1 The MC100ES6011 is a differential 1:2 fanout buffer. The ES6011 is ideal for applications requiring lower voltage. The 100ES Series contains temperature compensation. Small Outline Packages MC100ES6011EFR2 1 Download Model
Part Image Part Image 1 5V ECL ÷2 Divider Other MC100EL32DG 1 Download Model
Part Image Part Image 1 ECL 1:9 Differential Clock Driver Other MC100E111FNG 1 Download Model
Part Image Part Image 1 3.3V / 5V ECL 1:2 Differential Fanout Buffer Other MC100EP11DG 1 Download Model
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MC100ES6210AC Renesas Electronics
1 The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3GHz. The device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical, differential ECL/ PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10nF capacitor, the MC100ES6210 can be driven by single-ended ECL/PECL signals utilizing Quad Flat Packages MC100ES6210AC 1 Download Model
Part Image Part Image 1 Open Input Default State; 240 ps Typical Propagation Delay; Q Outputs will default LOW with inputs open or at VEE; Maximum Frequency > 3 GHz Typical; PECL Mode Operating Range: VCC= 2.375 V to 3.8 V with VEE= 0 V; NECL Mode Operating Range: VCC= 0 V with VEE= -2.375 V to -3.8 V; LVDS Input Compatible Small Outline Packages MC100LVEP11DTG 1 Download Model
Part Image Part Image 1 250 ps Typical Propagation Delay; Maximum Frequency > 3 Ghz Typical; NECL Mode Operating Range: VCC=0 V with VEE = -3.0V to -5.5V; PECL mode Operating Range: 3.0V to 5.5V VCC with VEE = 0V; Open Input Default State; Pb-Free Packages are Available Quad Flat No-Lead MC100EP101MNG 1 Download Model
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