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Image Part Number D.S Description Package Category Prices / Stock Model Action
Image Part Number D.S Description Package Category Prices / Stock Model Action
Part Image Part Image 1 Q Output will default HIGH with inputs open; PNP LVTTL Inputs for Minimal Loading; 350ps Typical Propagation Delay; Maximum Frequency > 1.0GHz; The 100 Series Contains Temperature Compensation; Operating Range: VCC= 3.0 V to 3.6 V; VEE= -3.6 V to -3.0 V; GND = 0 V; Pb-Free Packages are Available Small Outline Packages MC100EPT24DTG 1 Download Model
Part Image Part Image 1 Phase Frequency Detector IC 2GHz 1 8-SOIC (0.154", 3.90mm Width),3V ~ 3.6V -40°C ~ 85°C Small Outline Packages MC100EP140DR2G 1 Download Model
Part Image Part Image 1 Operating Range V CC = 3.0V to 3.6V with GND = 0; Q Output will default HIGH with inputs open; 390ps Typical Propagation Delay; Maximum Frequency > 1 Ghz Typical; PNP TTL Inputs for Minimal Loading Small Outline Packages MC100EPT20DTG 1 Download Model
Part Image Part Image 1 550 ps Typical Propagation Delay; PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V; Open Input Default State; Safety Clamp on Clock Inputs; Internal TCbar Feedback (Gated); Differential Clock Input; VBB Output; Fully Synchronous Counting and TCbar Generation; Asynchronous Master Reset; Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016; Addition of COUT and COUTbar; 8-bit; Pb-Free Packages are Available Quad Flat Packages MC100EP016AFAG 1 Download Model
Part Image Part Image 1 NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V; PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V ; Maximum Frequency > 3 GHz Typical; 220 ps Typical Propagation Delay; Open Input Default State; Safety Clamp on Inputs; Q Outputs Will Default LOW with Inputs Open or at VEE Small Outline Packages MC100EP11DR2G 1 Download Model
Part Image Part Image 1 330ps Typical Propagation Delay; Maximum Frequency > 4 GHz Typical; PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V; NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V; Q Output will default LOW with inputs open or at VEE; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available Small Outline Packages MC100EP52DTG 1 Download Model
Part Image Part Image 1 670 ps Typical Propagation Delay; ESD Protection: >2 KV HBM, >200 V MM; The 100 Series Contains Temperature Compensation; Operating Range: VCC = 4.75 V to 5.25 V; VEE = -4.2 V to -5.5 V; GND= 0 V; Internal Input Pulldown Resistors; Q Output will Default LOW with Inputs Open or at VEE; Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34; Transistor Count = 282 devices; Pb-Free Packages are Available Small Outline Packages MC100EL91DWG 1 Download Model
Part Image Part Image 1 NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V; PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V ; Maximum Frequency > 3 GHz Typical; 220 ps Typical Propagation Delay; Open Input Default State; Safety Clamp on Inputs; Q Outputs Will Default LOW with Inputs Open or at VEE Small Outline Packages MC100EP11DTG 1 Download Model
Part Image Part Image 1 Q Output will default LOW with inputs open or at GND; 24mA TTL outputs; Maximum Frequency > 275 MHz Typical; 1.1ns Typical Propagation Delay; Operating Range: VCC = 3.0 V to 3.6 V; VEE = -5.5 V to -3.0 V; GND = 0 V; VBB Output; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available Small Outline Packages MC100EPT25DG 1 Download Model
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MC100ES6254AC Renesas Electronics
1 MC100ES6254 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6254 are primary clock distribution, switching and loopback systems of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. Primary purpose of the MC100ES6254 is high-speed clock switching applications. In addition, the MC100ES6254 can Quad Flat Packages MC100ES6254AC 1 Download Model
Part Image Part Image 1 LVTTL/LVCMOS to LVECL Translator, 1 Func, Complementary Output, ECL, PDSO8 Small Outline Packages MC100EPT24DG 1 Download Model
Part Image Part Image 1 MC100EP140DG, Phase Frequency Detector 2.1GHz 5 8-Pin SOIC Small Outline Packages MC100EP140DG 1 Download Model
Part Image Part Image 1 ON Semiconductor MC100EP33DG, Clock Divider ECL ECL 2-Input Single Ended 8-Pin SOIC Small Outline Packages MC100EP33DG 1 Download Model
Part Image Part Image 1 Prescaler, 100EL Series, 1-Func, ECL, PDSO8 Small Outline Packages MC100EL33DG 1 Download Model
Part Image Part Image 1 MC100EP195MNG, Delay Line Circuit, 1024-Taps 12.2ns 10-Input, 32-Pin QFN Quad Flat No-Lead MC100EP195MNG 1 Download Model
Part Image Part Image 1 Translation - Voltage Levels 3.3V/5V Triple ECL Small Outline Packages MC100EP90DT 1 Download Model
Part Image Part Image 1 ONSEMI - MC100LVEL51DG - Flip-Flop, D, 475 ps, 2.8 GHz, 50 mA, SOIC Small Outline Packages MC100LVEL51DG 1 Download Model
Part Image Part Image 1 TTL/CMOS to PECL Translator, 2 Func, Complementary Output, ECL100K, PDSO8 Small Outline Packages MC100ELT22DTG 1 Download Model
Part Image Part Image 1 PECL to TTL Translator, 1 Func, True Output, ECL, PDSO8 Small Outline Packages MC100ELT21DTG 1 Download Model
Part Image Part Image 1 ON Semiconductor MC100EP445MNG, Octal Demultiplexer, Converter, 1-of-8, 32-Pin QFN Quad Flat No-Lead MC100EP445MNG 1 Download Model
Part Image Part Image 1 Flip-Flops 5V ECL 4-Bit D-Type Plastic Leaded Chip Carrier MC100E131FNG 1 Download Model
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MC100ES6210ACR2 Renesas Electronics
1 The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3GHz. The device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical, differential ECL/ PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10nF capacitor, the MC100ES6210 can be driven by single-ended ECL/PECL signals utilizing Quad Flat Packages MC100ES6210ACR2 1 Download Model
Part Image Part Image 1 PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V; 350ps Typical Propagation Delay; NECL Mode Operating Range: VCC= 0 V with VEE= –3.0 V to –5.5 V; Q Output will default LOW with inputs open or at VEE; Maximum Frequency > 4 GHz Typical; Open Input Default State; Safety Clamp on Inputs; Pb-Free Packages are Available Other MC100EP32DG 1 Download Model
Part Image Part Image 1 580 ps Typical Propagation Delays; ESD Protection: >2 KV HBM; 1100MHz Flip-Flop Toggle Frequency; The 100 Series Contains Temperature Compensation; PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V; NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V; Internal Input Pulldown Resistors; Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; Flammability Rating: UL-94 code V-0 @ 1Ǟ", Oxygen Index 28 to 34; Transistor Count = 313 devices; Pb-Free Packages are Available Small Outline Packages MC100LVEL29DWG 1 Download Model
Part Image Part Image 1 Q Output will default LOW with inputs open or at GND; 1.5ns Typical Propagation Delay; Maximum Operating Frequency > 275MHz; 24mA LVTTL Outputs; Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V; Open Input Default State; Pb-Free Packages are Available Small Outline Packages MC100EPT23DR2G 1 Download Model
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